View AD7617_8862477.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16-channel das with 14-bit, bipolar input, dual simultaneous sampling adc data sheet AD7617 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2017 analog devices, inc. all rights reserved. technical support www.analog.com features 16-channel, dual, simultaneously sampled inputs independently selectable channel input ranges true bipolar: 10 v, 5 v, 2.5 v single 5 v analog supply and 2.3 v to 3.6 v v drive supply fully integrated data acquisition solution analog input clamp protection input buffer with 1 m analog input impedance first-order antialiasing analog filter on-chip accurate reference and reference buffer dual 14-bit sar adc throughput rate: 2 1 msps per channel pair oversampling capability with digital filter flexible sequencer with burst mode flexible parallel/serial interface spi/qspi/microwire/dsp compatible optional crc error checking hardware/software configuration performance 85.3 db typical snr at 500 ksps (2 oversampling) 85 db typical snr at 1 msps ?103 db typical thd at 10 v range 0.3 lsb inl (typical), 0.99 lsb dnl (maximum) 8 kv esd analog input pins only on-chip self detect function 80-lead lqfp package applications power line monitoring protective relays multiphase motor control instrumentation and control systems data acquisition systems (dass) general description the AD7617 is a 14-bit, das that supports dual simultaneous sampling of 16 channels. the AD7617 operates from a single +5 v supply and can accommodate 10 v, 5 v, and 2.5 v true bipolar input signals while sampling at throughput rates up to 1 msps per channel pair with 85 db signal-to-noise ratio (snr). higher snr performance can be achieved with the on-chip oversampling mode (85.3 db for an oversampling ratio (osr) of 2). the input clamp protection circuitry can tolerate voltages up to 21 v. the AD7617 has 1 m analog input impedance, regardless of sampling frequency. the single-supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. the device contains analog input clamp protection, a dual, 14-bit charge redistribution successive approximation register (sar) analog-to-digital converter (adc), a flexible digital filter, a 2.5 v reference and reference buffer, and high speed serial and parallel interfaces. the AD7617 is serial peripheral interface (spi)/qspi?/dsp/microwire compatible. functional block diagram figure 1. AD7617 functional block diagram 1 6077-001 r fb 1m ? 1m ? r fb first- order lpf r fb 1m ? 1m ? r fb first- order lpf v0a v 0agnd r fb 1m ? 1m ? r fb v7a v 7agnd v0b v 0bgnd v7b v 7bgnd 9:1 mux busy convst control inputs clk osc refinout refsel ser/par ser1w osr digital filter 2.5v ref refcap notes 1. multifunction pins, such as db15/os2, are referred to by a single function of the pin, for example, db15, when only that function is relevant. refer to the pin configuration and function descriptions section for more information. serial regcap regcapd 1.8v dldo v cc AD7617 9:1 mux 14-bit sar 14-bit sar os2 to os0 v drive v cc aldo 2:1 mux hw_rngsel0, hw_rngsel1 chsel2 to chsel0 seqen flexible sequencer burst reset agnd dgnd db15 to db0 sdox/sdi parallel first- order lpf r fb 1m ? 1m ? r fb first- order lpf 1.8v aldo clamp clamp clamp clamp clamp clamp clamp clamp
AD7617* product page quick links last content update: 08/04/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7616/ad7616-p evaluation board documentation application notes ? an-1409: achieving pseudosimultaneous sampling by using the ad7616 flexible sequencer and burst mode ? an-1416: setup example for configuring the ad7616 for high dynamic range applications data sheet ? AD7617: 16-channel das with 14-bit, bipolar input, dual simultaneous sampling adc data sheet user guides ? ug-1012: evaluating the ad7616/ad7616-p 16-channel das with 16-bit, bipolar input, dual simultaneous sampling adc software and systems requirements ? ad7616 no-os/hdl drivers tools and simulations ? ad7616/AD7617 ibis model design resources ? AD7617 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD7617 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
AD7617 data sheet rev. 0 | page 2 of 51 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 6 ? absolute maximum ratings .......................................................... 10 ? thermal resistance .................................................................... 10 ? esd caution ................................................................................ 10 ? pin configuration and function descriptions ........................... 11 ? typical performance characteristics ........................................... 15 ? terminology .................................................................................... 21 ? theory of operation ...................................................................... 23 ? converter details ........................................................................ 23 ? analog input ............................................................................... 23 ? adc transfer function ............................................................. 24 ? internal/external reference ...................................................... 24 ? shutdown mode .......................................................................... 25 ? digital filter ................................................................................ 25 ? applications information .............................................................. 26 ? functionality overview ............................................................. 26 ? power supplies ............................................................................ 26 ? typical connections .................................................................. 26 ? device configuration ..................................................................... 28 ? operational mode ...................................................................... 28 ? internal/external reference ...................................................... 28 ? digital interface .......................................................................... 28 ? hardware mode .......................................................................... 28 ? software mode ............................................................................ 29 ? reset functionality..................................................................... 29 ? pin function overview ............................................................. 30 ? digital interface .............................................................................. 31 ? channel selection ....................................................................... 31 ? parallel interface ......................................................................... 32 ? serial interface ............................................................................ 33 ? sequencer ........................................................................................ 36 ? hardware mode sequencer ....................................................... 36 ? software mode sequencer ......................................................... 36 ? burst sequencer .......................................................................... 37 ? diagnostics ...................................................................................... 39 ? diagnostic channels .................................................................. 39 ? interface self test ....................................................................... 39 ? crc .............................................................................................. 39 ? register summary .......................................................................... 41 ? addressing registers .................................................................. 42 ? configuration register .............................................................. 43 ? channel register ........................................................................ 44 ? input range registers ................................................................ 45 ? sequencer stack registers ......................................................... 49 ? status register ............................................................................. 50 ? outline dimensions ....................................................................... 51 ? ordering guide .......................................................................... 51 ? revision history 7/2017revision 0: initial version
data sheet AD7617 rev. 0 | page 3 of 51 specifications v ref = 2.5 v external/internal, v cc = 4.75 v to 5.25 v, v drive = 2.3 v to 3.6 v, sampling frequency ( f sample ) = 1 m sps, t a = ?40c to +125c , unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit dynamic performance f in = 1 khz sine wave , unless otherwise noted signal - to - noise ratio (snr) 1 , 2 no o versampling , 10 v range 8 4.5 85 db osr = 2 , 10 v range , 3 f sample = 500 ksps 85.3 db osr = 4 , 10 v range 3 85.5 db no oversampling , 5 v r ange 8 4 84.5 db no oversampling , 2.5 v range 8 3 8 3.5 db signal - to - noise - and - distortion (sinad) 1 no oversampling , 10 v range 84 84.5 db no oversampling , 5 v range 8 3.5 8 4 db no oversampling , 2.5 v range 8 2.5 8 3.5 db dynamic range no oversampling , 10 v range 85.5 db no oversampling , 5 v range 85.1 db no oversampling , 2.5 v range 84.5 db total harmonic distortion (thd) 1 no oversampling, 10 v range ?103 ? 93.5 db no oversampling, 5 v range ?100 db no oversampling, 2.5 v range ? 97 db peak harmonic or spurious noise 1 ?103 db intermodulation distortion (imd) 1 fa = 1 khz, fb = 1.1 khz second - order terms ?10 5 db third - order terms ?1 13 db channel to channel isolation 1 f in on unselected channels up to 5 khz ?106 db analog input filter full power bandwidth ?3 db , 10 v range 39 khz ?3 db, 5 v/ + 2.5 v range 33 khz ?0.1 db 5.5 khz phase delay 1 , 3 10 v range 4. 4 6 s 5 v range 5 s 2.5 v range 4.9 s drift 1 , 3 10 v range 0.55 + 5 ns/ c matching (d ual simultaneous pair) 1 , 3 10 v range 4.4 100 ns 5 v range 4.7 ns 2.5 v range 4.1 ns dc accuracy resolution no missing codes 1 4 bits differential nonlinearity (dnl) 1 0. 1 0.99 lsb 4 integral nonlinearity (inl) 1 0.3 1 lsb total unadjusted error (tue) 10 v range 1.5 lsb 5 v range 2 lsb 2.5 v range 2.5 lsb positive full - scale error (pfs) 5 external r eference 10 v range 1.25 8 lsb 5 v range 1 lsb 2.5 v range 0.5 lsb internal r eference 10 v range 1.25 lsb
AD7617 data sheet rev. 0 | page 4 of 51 parameter test conditions/comments min typ max unit drift 3 external reference 2 5 ppm/c internal reference 3 10 ppm/c matching 1 10 v range 1 3 lsb 5 v range 1 lsb 2.5 v range 1 lsb bipolar zero code error 1 10 v range 0.15 2.5 lsb 5 v range 0.2 2.5 lsb 2.5 v range 0.7 3.5 lsb drift 3 10 v range 1.5 21 v/c 5 v range 1 v/c 2.5 v range 0.5 v/c matching 1 10 v range 0.5 2.5 lsb 5 v range 0.75 lsb 2.5 v range 0.75 lsb negative full-scale (nfs) error 1, 5 external reference 10 v range 1 8 lsb 5 v range 0.75 lsb 2.5 v range 1.5 lsb internal reference 10 v range 1 lsb drift 3 external reference 2 5 ppm/c internal reference 4 10 ppm/c matching 1 10 v range 1 3 lsb 5 v range 1 lsb 2.5 v range 2 lsb analog input input voltage ranges software/hardware selectable, 10 v range 10 v software/hardware selectable, 5 v range 5 v software/hardware selectable, 2.5 v range 2.5 v analog input current 10 v range, see figure 34 10.5 a 5 v range, see figure 34 6.5 a 2.5 v range, see figure 34 4 a input capacitance 6 10 pf input impedance see the analog input section 0.85 1 m input impedance drift 3 25 ppm/c reference input/output reference input voltage range see the adc transfer function section 2.495 2.5 2.505 v dc leakage current 1 a input capacitance 6 refsel = 1 7.5 pf reference output voltage measured at refinout 2.495 2.505 v reference temperature coefficient 3 2 15 ppm/c logic inputs input voltage high (v inh ) v drive = 2.7 v to 3.6 v 2 v v drive = 2.3 v to 2.7 v 1.7 v low (v inl ) v drive = 2.7 v to 3.6 v 0.8 v v drive = 2.3 v to 2.7 v 0.7 v input current (i in ) 1 a input capacitance (c in ) 6 5 pf
data sheet AD7617 rev. 0 | page 5 of 51 parameter test conditions/comments min typ max unit logic outputs output voltage high (v oh ) i source = 100 a v drive ? 0.2 v low (v ol ) i sink = 100 a 0.4 v floating state leakage current 0.005 1 a floating state output capacitance 6 5 pf output coding twos complement conversion rate conversion time per channel pair 0.5 s acquisition time per channel pair 0.5 s throughput rate per channel pair 1 msps power requirements v cc 4.75 5.25 v v drive 2.3 3.6 v i vcc normal mode static 37 57 ma operational f sample = 1 msps 42 65 ma shutdown mode 28 a i drive digital inputs = 0 v or v drive normal mode static 0.3 0.75 ma operational f sample = 1 msps 2.4 3.2 ma shutdown mode 20 a power dissipation normal mode static 185 300 mw operational f sample = 1 msps 230 3 5 0 mw shutdown mode 0. 25 mw 1 see the terminology section. 2 the user can achieve 85.3 db snr by enabli ng oversampling. th e values are valid for manual mode. in burst mode, values degrade by ~1 db. 3 not production tested. sample tested duri ng initial release to ensure compliance. 4 lsb means least significant bit. with a 2.5 v input range, 1 lsb = 305.175 v. with a 5 v input range, 1 lsb = 610.351 v. with a 10 v input range, 1 lsb = 1.220 mv. 5 positive and n egative full - scale error for the internal reference excludes reference errors. 6 supported by simulation data.
AD7617 data sheet rev. 0 | page 6 of 51 timing specification s universal timing specifications v cc = 4.75 v to 5.25 v, v drive = 2.3 v to 3.6 v, v ref = 2.5 v external reference/internal reference, t a = ? 40 c to + 125c , unless otherwise noted. interface timing tested using a load capacitance (c load ) of 30 pf , dependent on v drive and load capacitance for serial interface (see table 15). table 2 . parameter 1 min typ max unit description t cycle 1 s minimum time between consecutive convst rising edges (excluding burst and oversampling modes) t conv_low 50 ns convst low pulse width t conv_high 50 ns convst high pulse width t busy_delay 32 ns convst high to busy high (manual mode) t cs_setup 20 ns busy falling edge to cs falling edge setup time t ch_setup 50 ns channel select setup time in hardware mode for chselx t ch_hold 20 ns channel select hold time in hardware mode for chselx t conv 475 520 ns conversion time for the selected channel pair t acq 480 ns acquisition time for the selected channel pair t quiet 50 ns cs rising edge to next convst rising edge t reset _low partial r eset 40 500 ns partial reset low pulse width full reset 1.2 s full reset low pulse width t device_setup partial reset 50 ns time between partial reset high and convst rising edge full reset 15 ms time between full reset high and convst rising edge t write partial reset 50 ns time between partial reset high and cs for write operation full reset 240 s time between full reset high and cs for write operation t reset _wait 1 ms time between stable v cc /v drive and release of reset (see figure 51) t reset _setup time prior to release of reset that queried hardware inputs must be stable for (see figure 51) partial reset 10 ns full reset 0.05 ms t reset _hold time after release of reset that queried hardware inputs must be stable for (see figure 51) partial reset 10 ns full reset 0.24 ms 1 not production tested. sample tested during initial release to ensure compliance. figure 2 . universal timing diagram across all interfaces convst busy cs ch x c h y chsel0 to chsel2 t busy_delay t conv_high t quiet t cs_setup t ch_setup t ch_hold hardware mode only 16077-102 t cycle t conv_low t conv t acq
data sheet AD7617 rev. 0 | page 7 of 51 figure 3 . reset timing p arallel mode timing specifications table 3 . parameter min typ max nit description t rd _setup 10 ns cs falling edge to rd falling edge setup time t rd _hold 10 ns rd rising edge to cs rising edge hold time t rd _high 10 ns rd high pulse width t rd _low 30 ns rd low pulse width t dout_setup 30 ns data access time after falling edge of rd t dout_3state 1 1 ns cs rising edge to db x high impedance t wr _setup 10 ns cs to wr setup time t wr _high 20 ns wr high pulse width t wr _low 30 ns wr low pulse width t wr _hold 10 ns wr hold time t din_setup 30 ns configuration data to wr setup time t din_hold 10 ns configuration data to wr hold time t conf_settle 2 0 ns configuration data settle time, wr rising edge to convst rising edge v cc v drive reset convst busy cs mode range setting in hw mode ch x ch y ch z ac q x c o n v x acq y conv y reset_wait device_setup t write all modes hardware mode only refsel ser/par, ser1w hw_rngsel0, hw_rngsel1 crcen, burst seqen, os0 to os2 chsel0 to chsel2 adc internal action reset_setup reset_hold reset_low 16077-103
AD7617 data sheet rev. 0 | page 8 of 51 figure 4. parallel read timing diagram figure 5. parallel write timing diagram serial mode timing specifications table 4. parameter min typ max unit description f sclk 1 40/50 mhz sclk frequency t sclk 1/f sclk minimum sclk period t sclk_setup 1 10.5 ns cs to sclk falling edge setup time, v drive above 3 v 13.5 ns cs to sclk falling edge setup time, v drive above 2.3 v t sclk_hold 10 ns sclk to cs rising edge hold time t sclk_low 8 ns sclk low pulse width t sclk_high 9 ns sclk high pulse width t dout_setup 1 9 ns data out access time after sclk rising edge, v drive above 3 v 11 ns data out access time after sclk rising edge, v drive above 2.3 v t dout_hold 4 ns data out hold time after sclk rising edge t din_setup 10 ns data in setup time before sclk falling edge t din_hold 8 ns data in hold time after sclk falling edge t dout_3state 10 ns cs rising edge to sdox high impedance 1 dependent on v drive and c load (see table 15). 16077-104 convst busy cs rd conv a conv b db0 to db15 t rd_hold t rd_high t dout_3state t rd_setup t rd_low t dout_setup convst cs wr write reg 1 write reg 2 db0 to db15 t conf_settle t din_hold t din_setup t wr_hold t wr_setup 16077-105 t wr_high t wr_low
data sheet AD7617 rev. 0 | page 9 of 51 figure 6. serial timing diagram convst busy cs 1 2 3 141516 sclk db15 db14 db13 db15 db14 db13 db15 db14 db13 db2 db1 db0 db2 db1 db0 db2 db1 db0 sdoa sdob sdi t dout_setup t dout_hold t sclk_setup t sclk t sclk_high t sclk_low t sclk_hold t din_hold t din_setup t dout_3state 16077-106
AD7617 data sheet rev. 0 | page 10 of 51 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5 . parameter rating v cc to agnd ?0.3 v to +7 v v drive to agnd ?0.3 v to v cc + 0.3 v analog input voltage to agnd 1 2 1 v digital input voltage to agnd ?0.3 v to v drive + 0.3 v digital output voltage to agnd ?0.3 v to v drive + 0.3 v refin out to agnd ?0.3 v to v cc + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c soldering reflow pb/s n temperature (10 sec to 30 sec) 240 (+0)c pb - free temperature 260 (+0)c esd all pins except analog inputs 2 kv analog input pins only 8 kv 1 transient curren ts of up to 100 ma do not cause s ilicon c ontrolled r ectifier ( scr ) latch - up. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operating environment. close attention to pcb thermal design is required. ja is the natural convection junction to ambien t thermal resistance measured in a one cubic foot sealed enclosure. jc is the junction to case thermal resistance. table 6 . thermal resistance package type ja jc unit st -80 -2 1 41 7.5 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51 . esd caution
data sheet AD7617 rev. 0 | page 11 of 51 pin configuration an d function descripti ons figure 7 . pin configuration table 7 . pin function descriptions pin no. type 1 mnemonic 2 description 1 ai gnd v4bgnd analog input ground pin. this pin corresponds to analog input pin v4b. 2 ai v4b analog input for channel 4 , adc b. 3 ai gnd v5bgnd analog input ground pin. this pin corresponds to analog input pin v5b. 4 ai v5b analog input for channel 5 , adc b. 5, 16, 29, 72 gnd agnd analog supply ground pin . 6, 15, 30, 71 p v cc analog supply voltage, 4.7 5 v to 5.25 v. this supply voltage is applied to the internal front - end amplifiers and to the adc core. decouple t hese pins t o agnd using 0.1 f and 10 f capacitor s in parallel. 7 ai v6b analog input for channel 6 , adc b. 8 ai gnd v6bgnd analog input ground pin. this pin corresponds to analog input pin v6b. 9 ai v7b ana log input for channel 7 , adc b. 10 ai gnd v7bgnd analog input ground pin. this pin corresponds to analog input pin v7b. 11 ai gnd v7agnd analog input ground pin. this pin corresponds to analog input pin v7a. 12 ai v7a analog input for channel 7 , adc a. 13 ai gnd v6agnd analog input ground pin. this pin corresponds to analog input pin v6a. 14 ai v6a analog input for channel 6 , adc a. 17 ai v5a analog input for channel 5, adc a. 18 ai gnd v5agnd analog input ground pin. this pin corresponds to analog input pin v5a. 19 ai v4a analog input for channel 4, adc a. 20 ai gnd v4agnd analog input ground pin. this pin corresponds to analog input pin v4a. 16077-005 v4 b g n d v4 b v5 b g n d v5 b a g n d v c c v6 b v6 b g n d v7 b v7 b g n d v7 a g n d v7 a v6 a g n d v6 a v c c a g n d v5 a v5 a g n d v4 a v4 a g n d db12/ sd o a db13/os0 db14/os1 db15/os2 db11/ sd o b db10/ sd i db9 db8 r eg capd r eggndd d g n d v dri v e db7 db6 db5 / crcen db3 db2 db1 db0 v3 a g n d v3 a v2 a g n d v2 a v1 a g n d v1 a v0 a g n d v0 a a g n d v c c r ef cap r ef g n d r ef i n o u t r ef i n o u t g n d r ef sel seq en h w _ rng sel 1 h w _ rng sel 0 v3 b g n d v3 b v2 b g n d v2 b v1 b g n d v1 b v0 b g n d v0 b a g n d v c c r eg cap r eggn d c o n vst busy chsel 2 chsel 1 chsel 0 AD7617 top view (not to scale) r eset ser / pa r db4 / ser 1 w w r / burst sc l k / r d c s 2 3 4 7 6 5 1 8 9 1 0 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 1 1 5 9 5 8 5 7 5 4 5 5 5 6 6 0 5 3 5 2 5 1 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 5 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 anal og in pu t d ec o u pl i n g cap pi n po w er su ppl y g r o und pi n d igit a l i n pu t r ef er ence i n pu t /ou t pu t d igit a l i n pu t /ou t pu t d igit a l o u t pu t
AD7617 data sheet rev. 0 | page 12 of 51 pin no. type 1 mnemonic 2 description 21 ai gnd v3agnd analog input ground pin. this pin corresponds to analog input pin v3a. 22 ai v3a analog input for channel 3 , adc a. 23 ai gnd v2agnd analog input ground pin. this pin corresponds to analog input pin v2a. 24 ai v2a analog input for channel 2 , adc a . 25 ai gnd v1agnd analog input ground pin. this pin corresponds to analog input pin v1a. 26 ai v 1 a analog input for channel 1 , adc a . 27 ai gnd v0agnd analog input ground pin. this pin corresponds to analog input pin v0a. 28 ai v0a analog input for channel 0 , adc a . 31 cap refcap referenc e buffer output force/sense pin . decouple t his pin to refgnd using a low effective series resistance ( esr ) , 10 f , x5r ceramic capacitor , as close to the refcap pin as possible . the voltage on this pin is typically 4.096 v. 32 cap refgnd reference g round pi n. connect t his pin to agnd. 33 ref refinout reference i nput/reference o utput. the on - chip reference of 2.5 v is available on this pin for external use when the refsel pin is set to logic high. alternatively, the internal reference can be disabled by setting the ref s el pin to logic low, and an external reference of 2.5 v can be applied to this input. decoupling is required on this pin for both the internal and extern al reference options. connect a 100 nf, x7 r capacitor between the refinout and refinoutgnd pins , as close to the refinout pin as possible. if using an external reference, connect a 10 k series resistor to this pin to band limit the reference signal. 34 cap refinoutgnd reference input, reference output g round p in. 35 di refsel internal/ e xternal r eference s election i nput. refsel is a l ogic input. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled , and an external reference voltage must be applied to the refinout pin. the s ignal state is latched on the release of a full reset and requires an additional full reset to reconfigure. 36 di reset reset input. connect a 100 pf capacitor between reset and ground. full and partial reset options are available. the type of reset is determined by the length of the reset pulse. keeping reset low places the device into shutdown mode. see the r eset functionality section for further details. 37 di seqen channel sequencer enable input ( h ardware m ode o nly). when seqen is tied low, the sequencer is disabled. when seqen is high , the sequencer is enabled (with restricted functionality in hardware mode). see the s equencer section for further details. the signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. in software mode , this pin must be connected to dgnd. 38, 39 di hw_rngsel1, hw_rngsel0 hardware/ software mode selection, hardware mode range select inputs . hardware/software mode selection is latched at full reset. range selection in hardware mode is not latched. hw_rngsel x = 00 : s oftware mode ; the AD7617 is configured via the software registers. hw_rngselx = 01 : h ardware mode ; a nalog input range is 2.5 v. hw_rngselx = 10 : h ardware mode ; a nalog input range is 5 v. hw_rngselx = 11 : h ardware mode ; a nalog input range is 10 v. 40 di ser/ par serial /parallel interface selection input. logic input. if this pin is tied to logic low, the paralle l interface is selected. if this pin is tied to logic high, the serial interface is selected. the signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. 41, 42, 43, 44 do/di db 0 , db1, db2, db3 parallel output/input data bit 0 to data bit 3 . in parallel mode , db2 is the lsb of the 14 - bit conversion result and db0 and db1 output zero. in software parallel mode, db0, db1, db2, and db3 are the four lsbs of a register write/read operation. in hardware parallel mode, db0 and db1 can be left floating or pul l ed to dgnd via a 10 k pull - down resistor. refer to the parallel interface section for further details. in serial mode , these pins must be tied to dgnd.
data sheet AD7617 rev. 0 | page 13 of 5 1 pin no. type 1 mnemonic 2 description 45 do/di db4/ ser1w parallel output/input data bit 4/serial output selection. in parallel mode, this pin acts as a three - state parallel digital output/input pin. refer to the parallel interface section for further details. in serial mode , this pin determines whether the serial output operates over sdoa and sdob or just sdoa. when ser1w is low , the serial output operates over sdoa only. when ser1w is high , the serial output operates over both sdoa and sdob. the signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. 46 do/di db5/ crcen pa rallel output/input data bit 5 / cyclic redundancy c heck ( crc ) enable input. in parallel mode, this pin acts as a three - stat e parallel digital input/output. while in serial mode, this pin acts as a crc enable input. the crcen signal state is latched on the release of a full reset, and requires an additional full rese t to reconfigure. refer to the digital interface section for further details. in serial mode, when crcen is low, there is no crc word following the conversion results; when crcen is high, an extra crc word follow s the last conversion word configured by chselx . see the crc section for further details. in software mode , this pin must be connected to dgnd. 47, 48 do/di db6 , db7 parallel output/input data bit 6 and data bit 7 . when ser/ par = 0, these pin s act as three - state parallel digital input/output s . refer to the parallel interface section for further details. in serial mode, when s er/ par = 1 , these pins must be tied to dgnd . 49 p v drive logic power supply input. the voltage (2.3 v to 3.6 v) supplied at this pin determines the operating voltage of the interface. this pin is nominally at the same supply as the supply of the host interface. decouple this pin with 0.1 f and 10 f capacitor s in parallel. 50 gnd dgnd digital ground. this pin is the ground reference point for all digital circuitry on the AD7617 . the dgnd pin must connect to the dgnd plane of a system. 51 cap reggndd ground for the d igital low dropout ( ldo ) regulator c onnected to regcapd ( p in 52). 52 cap regcapd decoupling capacitor pin for voltage output from interna l digital regulator. decouple t his output pin separately to reggndd using a 10 f capacitor. the voltage at this pin is 1.8 9 v t ypical. 53, 54 do/di db8, db9 parallel output/input data bit 9 and data bit 8 . when ser/ par = 0, th e s e pin s act as three - state parallel digital input/output s . refer to the parallel interface section for further details. in serial mode, when ser/ par = 1 , these pins must be tied to dgnd . 55 do/di db10/sdi parallel output/input data bit db10/ serial data input . when ser/ par = 0, this pin acts as a three - state parallel digital input/output. refer to the parallel interface section for further details. in h ardware s erial mode , tie this pin to dgnd. in serial mode, when ser/ par = 1 , this pin acts as the data input of the spi interface . 56 do/di db11/sdob pa rallel output/input data bit 11/ serial data output b . when ser/ par = 0, this pin acts as a three - state parallel digital input/output. refer to the parallel interface section for further details. in serial mode, when ser/ par = 1 and db 4/ ser1w = 1, this pin functions as sdob and outputs serial conversion data. 57 do/di db12/ sdoa pa rallel output/input data bit 12/ serial data output a . when ser/ par = 0, this pin acts as a three - state parallel digital input/output. refer to the parallel interface section for further details. in serial mode, when ser/ par = 1 , this pin functions as sdoa and outputs serial conversion data. 58, 59, 60 do/di db 13/os0 , db14/os1, db15/os2 parallel output/input data bit 13, data bit 14, and data bit 15 /oversampling ratio s election. when ser/ par = 0 , the s e pin s act as three - state parallel digital input/output s . refer to the parallel interface section for further details. in serial hardware mode, these pins control the oversampling settings. the signal state is latched on the release of a full reset and requires an additional full reset to reconfigure. see the digital filter section for further details. in software serial mode , these pins must be connected to dgnd. 61 di wr /burst write/burst mode enable. in software parallel mode, this pin acts as wr for a parallel interface. in hardware parallel or serial mode, this pin enables burst mode. the signal state is latched on the release of a full reset, and requires an additional full re set to reconfigure. refer to the burst sequencer section for further information. in software serial mode , connect this pin to dgnd.
AD7617 data sheet rev. 0 | page 14 of 51 pin no. type 1 mnemonic 2 description 62 di sclk/ rd serial clock input /parallel data read control input. in serial mode, this pin acts as the serial clock input for data transfers. the cs falling edge takes the sdoa and sdob data output lines out of three - state and c locks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the sdoa and sdob serial data outputs. when both cs and rd are logic low in parallel mode, the output bus is enabled. 63 di cs chip select. this active low logic input frames the data transfer. in parallel mode, when both cs and rd are logic low, the db x output bus is enabled , and the conversion result is output on the parallel data bus lines. i n serial mode, cs frames the serial read transfer and clocks out the msb of the serial output data. 64, 65, 66 di chsel 0, chsel1, chsel2 channel selection input 0 to input 2 . in hardware mode, these inputs select the input channels for the next conversion in c hannel g roup a and channel group b. for example, chselx = 0x000 select s v0a and v0b for the next conversion; chselx = 0x001 selects v 1a and v1b for the next conversion . in software mode , these pins must be connected to dgnd. 67 do busy busy output. this pin transitions to a logic high after a convst rising edge and indicates that the conversion process started. the busy output remains high until the conversion process for the current selected channels complete s . the falling edge of busy signals that the conversion data is being latched into the output data registers and is available to read. data must be read after busy returns to low. rising edges on convst have no effect while the busy signal is high. 68 di convst conversion start input for c hannel g roup a and channel group b. this logic input initiate s conversions on the analog input channels. a conversion initiates when convst transitions from low to high for the selected analog input pair. when burst mode and oversampling mode are disabled, every convst transition from low to high converts one channel pair. in sequencer mode, when burst mode or oversampling is enab led, a single convst transition from low to high is necessary to perform the required number of conversions. 69 cap reggnd internal analog regulator ground. this pin must connect to the agnd plane of a system. 70 cap regcap decoupling capacitor pin for voltage output f rom internal analog regulator. decouple t his output pin separately to reggnd using a 10 f capacitor. the voltage at this pin is 1.8 7 v typical. 73 ai v0b analog input for channel 0 , adc b. 74 ai gnd v0bgnd analog input ground pin. this pin corresponds to analog input pin v0b. 75 ai v1b analog input for channel 1 , adc b. 76 ai gnd v1bgnd analog input ground pin. this pin corresponds to analog input pin v1b. 77 ai v2b analog input for channel 2 , adc b. 78 ai gnd v2bgnd analog input ground pin. this pin corresponds to analog input pin v2b. 79 ai v3b analog input for channel 3 , adc b. 80 ai gnd v3bgnd analog input ground pin. this pin corresponds to analog input pin v3b. 1 ai is analog input, gnd is ground, p is power supply, cap is decoupling capacitor pin, ref is reference input/output, di is digital input, and do is digital output. 2 note that throughout this data sheet, multifunction pins, such as ser/ par , are referred to either by the entire pin name or by a single function of the pin, for example, ser, when only that function is relevant.
data sheet AD7617 rev. 0 | page 15 of 51 typical performance characteristics v ref = 2.5 v internal, v cc = 5 v, v drive = 3.3 v, f sample = 1 msps, f in = 1 khz t a = 25 c, unless otherwise noted. figure 8. fast fourier transform ( fft ) , 10 v range figure 9 . fft, 5 v range figure 10 . fft burst mode, 10 v range figure 11 . snr vs. temperature figure 12 . sinad vs. temperature figure 13 . thd vs. temperature ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 300 400 500 magnitude (db) frequenc y (khz) 0 snr = 85.1db sinad = 84.42db thd = ?103.41db n samples = 8192 f sample = 1msps 16077-308 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 0 200 300 400 500 magnitude (db) frequenc y (khz) snr = 84.47db sinad = 83.95db thd = ?103.41db n samples = 8192 f sample = 1msps 16077-309 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 0 20 30 40 50 60 magnitude (db) frequenc y (khz) snr = 85db sinad = 84.43db thd = ?107.4db n samples = 8192 f sample = 62.5ksps 16077-310 80 81 82 83 84 85 86 87 88 89 90 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 snr (db) temper a ture (c) 16077-3 1 1 10v range 5v range 2.5v range 80 81 82 83 84 85 86 87 88 89 90 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 sinad (db) temper a ture (c) 10v range 5v range 2.5v range 16077-312 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 1 10 125 thd (db) temper a ture (c) 10v range 5v range 2.5v range r source matched on vxx and vxxgnd inputs 16077-313
AD7617 data sheet rev. 0 | page 16 of 51 figure 14 . typical inl error , 10 v range figure 15 . typical inl error, 5 v range figure 16 . typical dnl error, 10 v range figure 17 . typical dnl error, 5 v range figure 18 . dc histo gram of codes at code center, 10 v range figure 19 . dc hist ogram of codes at code center, 5 v range ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 5000 10000 15000 in l error (lsb) code 16077-314 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 5000 10000 15000 in l error (lsb) code 16077-315 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 5000 10000 15000 dn l error (lsb) code 16077-316 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 5000 10000 15000 dn l error (lsb) code 16077-317 0 0 0 10000 20000 30000 40000 50000 60000 70000 8190 8191 8192 8193 number of hits code 10v range vxx and vxxgnd shorted together 65,537 samples 8127 57410 16077-318 0 20776 44759 2 0 10000 20000 30000 40000 50000 8190 8191 8192 8193 number of hits code 16077-319 5v range vxx and vxxgnd shorted together 65,537 samples
data sheet AD7617 rev. 0 | page 17 of 51 figure 20 . dc histo gram of codes at code center, 2.5 v range figure 21 . nfs error vs. temperature figure 22 . pfs error vs. temperature figure 23 . p fs/ n fs error vs. source resistance figure 24 . nfs/pfs error matching vs. temperature figure 25 . bipolar zero code error vs. temperature 0 20776 44759 2 0 10000 20000 30000 40000 50000 8190 8191 8192 8193 number of hits code 5v range vxx and vxxgnd shorted together 65,537 samples 16077-320 ? 10 ? 8 ? 6 ? 4 ? 2 0 2 4 6 8 10 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 1 10 125 nfs error (lsb) temper a ture (c) 10v range 5v range 2.5v range 16077-321 temper a ture (c) 10v range 5v range 2.5v range ? 10 ? 8 ? 6 ? 4 ? 2 0 2 4 6 8 10 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 1 10 125 pfs error (lsb) 16077-322 0 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0 20 40 60 80 10 pfs/nfs error (%fs) source resis t ance (m) nfs 10v nfs 5v nfs 2.5v pfs 10v pfs 5v pfs 2.5v 16077-323 0 0.5 1.0 1.5 2 2.5 3.0 3.5 4.0 4.5 5.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 1 10 125 nfs/pfs error m a tching (lsb) pfs 10v range nfs 10v range temper a ture (c) 16077-324 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 1 10 125 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 bipolar zero code error (lsb) 10v range 5v range 2.5v range temper a ture (c) 16077-325
AD7617 data sheet rev. 0 | page 18 of 51 figure 26 . bipolar zero code error matching vs. temperature figure 27 . thd vs. input frequency for various source impedances, 10 v range figure 28 . thd vs. input frequency f or various sou r ce impedances, 5 v range figure 29 . snr vs. input frequency for d ifferent oversampling rates, 10 v range figure 30 . snr vs. input frequency for d ifferent oversampling rates, 5 v range figure 31 . channel to channel isolation vs. interferer frequency 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 bipolar zero error m a tching (lsb) temper a ture (c) 10v range 5v range 2.5v range dc input 16077-326 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 1k 10k 100k thd (db) input frequency (hz) 0 1.2k 5.6k 10k 25k 50k 110k 16077-327 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 1k 10k 100k thd (db) input frequency (hz) 5v range r source matched on vxx and vxxgnd inputs 0 1.2k 5.6k 10k 25k 50k 110k 16077-328 80 81 82 83 84 85 86 87 100 1k 10k 100k snr (db) frequenc y (hz) no os osr 2 osr 4 osr 8 osr 16 osr 32 16077-329 80 81 82 83 84 85 86 87 100 1k 10k 100k snr (db) frequenc y (hz) no os osr 2 osr 4 osr 8 osr 16 osr 32 16077-330 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 0 5000 10000 15000 20000 25000 30000 channe l t o channe l isol a tion (db) interferer frequenc y (hz) 10v range 5v range 2.5v range 16077-231
data sheet AD7617 rev. 0 | page 19 of 51 figure 32 . phase delay vs. temperature figure 33 . internal reference voltage vs. temperature for various supply voltages figure 34 . analog input current vs. temperature for various supply voltages figure 35 . input impedance vs. temperature figure 36 . cmrr vs. ripple frequency figure psrr vs ripple freuenc 0 2 4 6 8 10 12 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 p h as e d e l a y ( s ) t e m p e r a t u r e (c) 10v range 5v range 2.5v range 16077-232 2.490 2.495 2.500 2.505 2.510 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 interna l reference vo lt age (v) temper a ture (c) 4.75v 5v 5.25v 16077-234 ?15 ?10 ?5 0 5 10 15 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 analog input current (a) temperature (c) + 10v i n pu t ?10 v i n pu t + 5 v i n pu t ?5v i n pu t + 2.5 v i np u t ?2.5 v i n pu t 16077-235 0.985 0.990 0.995 1.000 1.005 1.010 1.015 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 input impedance (m) temper a ture (c) 10v range 5v range 2.5v range 16077-335 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m cmrr (db) ripple frequenc y (hz) 10v range 5v range 2.5v range 16077-237 40 50 60 70 80 90 100 110 120 130 100 1k 10k 100k 1g psrr (db) ripple frequenc y (hz) 10v 5v 2.5v 16077-337
AD7617 data sheet rev. 0 | page 20 of 51 figure 38 . static/dynamic iv cc current vs. temperature figure 39 . dynamic v drive current vs. temperature figure 40 . static v drive current vs. temperature figur e 41 . iv cc cu rrent vs. sampling frequency 0 10 20 30 40 50 60 70 80 90 1 0 0 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) static/dynamic iv cc c u rr en t (m a ) st a t i c d yn a mi c 16077-238 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 dynamic v drive current (ma) temper a ture (c) ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 16077-239 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 static v drive current (ma) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) 16077-240 38 39 40 41 42 43 44 45 46 47 100 200 300 400 500 600 700 800 900 1000 iv cc current (ma) sampling frequenc y (ksps) 16077-241
data sheet AD7617 rev. 0 | page 21 of 51 terminology integral nonlinearity (inl) inl is t he maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the t ransfer function are zero scale a t ? lsb below the first code transition and full scale at ? ls b above the last code transition. differential nonlinearity (dnl) dnl is t he difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error bipolar zero code error is th e deviation of the mids cale transition (all 1s to all 0s) from the ideal , which is 0 v ? ? lsb. bipolar zero code error match ing bipolar zero code error match ing is t he absolute difference in bipolar zero code error between any two input channels. positive full - scale (pfs) error positive full - scale error is t he deviation of the actual last code transition from the ideal last code transition (10 v ? 1 ? lsb (9.999 54), 5 v ? 1 ? lsb ( 4.99977 ) , and 2.5 v ? 1? lsb ( 2 .4 998 9) ) after bipolar zero code error is adjusted out. the positive full - scale error includes the contribution from the internal reference buffer. positive full - scale error match ing positive full - scale error match ing is th e absolute difference in positive full - scale error between any two input channels. negative f ull - scale (nfs) error negative full - scale error is t he deviation of the first code transition from the ideal first code transition ( ? 10 v + ? lsb ( ? 9.999 8 5 ) , ? 5 v + ? lsb ( ? 4.99992) and ? 2.5 v + ? lsb ( ? 2.49996) ) after the bipolar zero code error is adjusted out. the negative full - scale error includes the contribution from the internal reference buffer. negative full - scale error match ing negative full - scale error match ing is t he absolute difference in negative full - scale error between any two inpu t channels. signal -to - noise - and - distortion ratio (sinad) sinad is the measured ratio of signal to noise and distortion at the output of the adc. the signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to hal f the sampling frequency (f s /2), including harmonics, but excluding dc. signal -to - noise ratio (snr) snr is the measured ratio of signal to noise at the output of the adc. the signal is the rms amplitude of the fundamental. nois e is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. the theoretical snr for an ideal n - bit converter with a sine wave input is given by snr = (6.02 n + 1.76) db therefore, for a 14 - bit converter, the snr is 86 db . total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels (db). peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. n ormally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. intermodulation distortion with inputs consisting of sine wave s at two frequencies, fa and fb, any active device with nonlinearities create s distortion products at the sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n is equal to 0. for example, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (db) . power supply rejection ratio (psr r ) variations in power supply affect the full - scale transition but not the linearity of the converter . power supply rejection is the maximum change in full - scale transition point due to a change in power supply voltage from the nominal value. the psrr is defined as the ratio of the power in the adc output at full - scale frequency, f, to the po wer of a 1 00 mv p - p sine wave applied to the v cc supply of the adc of f requency , f s . psrr (db) = 10log( pf / pf s ) where: pf is equal to the power at f r equency , f , in the adc output. pf s is equal to the power at f requency , f s , coupled onto the v cc supply.
AD7617 data sheet rev. 0 | page 22 of 51 ac common - mode rejection ratio (ac cmrr) ac cmrr is defined as the ratio of the power in the adc output at frequency, f, to the power of a sine wave applie d to the common - mode voltage of vx x and vx x gnd at frequency, f s . ac cmrr (db) = 10l og( pf / pf s ) where: pf is the power at frequency, f, in the adc output. pf s is the power at frequency, f s , in the adc output. channel to channel isolation channel to channel isolation is a measure of the level of crosstalk between all input channels. it is me asured by applying a full - scale sin e wave signal , up to 160 khz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 khz sine wave signal applied . phase delay phase delay is a measure of the absolute time delay between when an input is sampled by the converter and when the result associated with that sample is available to be read back from t he adc , including delay induced by the analog front end of the device . phas e delay drift phase delay drift is the change in phase delay per unit temperature across the entire operating temperature of the device. phase delay matching p hase delay matching is the maximum phase delay seen between any simultaneously sampled pair.
data sheet AD7617 rev. 0 | page 23 of 51 theory of operation converter details the AD7617 is a data acquisition system that employs a high speed, low power, charge redistribution, sar adc , and allow s dual simultaneous sam pling of 16 analog input channels. the analog inputs on the AD7617 can ac cept true bipolar input signals. analog input range options include 10 v, 5 v , and 2.5 v. the AD7617 operate s from a single 5 v suppl y. the AD7617 c ontain s input clamp protection, input signal scaling amplifiers, a first - order antialiasing filter, an on - c hip reference, a reference buffer , a dual high speed adc, a digital filter , a flexible sequencer , and high speed parallel and serial interfaces. the a d7617 can operate in hardware or software mode by controlling the hw_rngselx pins. in hardware mode , the AD7617 is configured by pin control. in software mode , the AD7617 is configured by the control registers accessed via the serial or parallel i nterface. analog input analog input channel selection the AD7617 contains dual , simultaneous sampling , 14- bit adcs. each adc has eight a nalog input channels for a total of 16 analog inputs. additionally , the AD7617 has on - chip diagnostic chann els to monitor the v cc supply and an on - chip adjustable low dropout regulator . channels can be selected for conversion by control of the chselx pins in hardware mode or via the channel register control in software mode. software mode is required to sample the diagnostic channels. chan nels can be selected dynamically or the AD7617 has an on - chip sequencer to allow the channels for conversion to be preprogrammed. in har dware mode , simultaneous sampling is limited to th e corresponding a or b channel , that is, channel v 0 a always sample s with channel v0 b . in software mode , it is possible to select any a channel with any b channel for simultaneous sampling. analog input ranges the AD7617 can handle true bipolar, single - ended input voltages. the logic level s on the range select pins, hw_rngsel 0 and hw_rng sel1 , determine the analog input range of all analog input channels. if both range select pins are tied to a logic low, the analog input range is determined in software mode via the input range r egisters ( see the r egist er summary section for more details ) . in software mode, it is possible to configure an individual analog input range per channel. table 8 . analog input range selection analog input range hw_rngsel 1 hw_rngsel 0 configured via the input range registers 0 0 2.5 v 0 1 5 v 1 0 10 v 1 1 in hardware mode, a logic change on th ese pin s has an imme diate effect on the analog input range; ho wever , there is typically a settling time of approximately 120 s in addition to the normal acquisition time requirement. the recommended practice is to hardwire the range select pin s accordin g to the desired input range for the system signals. analog input impedance the low drift analog input impedance of the AD7617 is 1 m? , a fixed input impedance that does not vary with the AD7617 sampling frequency. this high analog input impedance eliminates the need for a driver amplifier in front of the AD7617 , allowing direct connection to the source or the sensor. analog input clamp protection figure 42 shows the analog input circuitry of the AD7617 . each analog input of th e AD7617 contains clamp protection circuitry. despite single + 5 v supply operation, this analog input clamp protection allows an input o vervoltage of between ?20 v and +20 v . figure 42 . analog input circuitry figure 43 shows the input clamp current vs. source voltage characteristic of the clamp circuit. for source voltages between ? 20 v and +20 v , no current flows in the clamp circuit. for input voltages that are greater than + 2 0 v and less than ?20 v , the AD7617 clamp circuitry turns on. figure 43 . input protection clamp profile , input clamp current vs. source voltage place a series resistor on the analog input channels to limit the current to 10 ma for input voltages greater than + 2 0 v and less than ?20 v . in an application where there is a series resistance on an analog input channel, v x a or vx b , a corresponding resistance is required on the analog input ground channel, v x a gnd or vx b gnd (see figure 44 ). 1m? clamp vxx 1m? clamp vxxgnd first- order lpf r fb r fb 16077-006 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 ?30 ?20 ?10 0 10 20 30 input clam p current (ma) source vo lt age (v) powered off powered on 16077-243
AD7617 data sheet rev. 0 | page 24 of 51 if there is no correspond ing resistor on the v x a gnd or vx b gnd channel, an offset error occurs on that channel. use the input overvoltage clamp protection circuitry to protect the AD7617 against transient overvoltage events. it is not recom - mended to leave the AD7617 in a condition where the clamp protection circuitry is active in normal or power - down conditions for extended periods . figure 44 . input resistance matching on the a nalog input analog input antialiasing filter an analog antialiasing filter (a first - order butterworth) is also provided on the AD7617 . figure 45 and figure 46 show the frequency an d phase response, respectively, of the analog antialiasing filter. the typical corner frequency in the 10 v range is 39 khz, and 33 khz in the 5 v range. figure 45 . analog antialiasing filter frequency response figure 46 . analog antialiasing filter phase response adc transfer functio n the output coding of the AD7617 is twos c omplement. the code transitions occur midway between successive integer lsb values, that is, 1/2 lsb and 3/2 lsb. the lsb size is full - scale range 16,384 for the AD7617 . the ideal transfer characteristic s for the AD7617 are shown in figure 47 and figure 9 . the lsb size is dependent on the analog input range selected. figure 47 . transfer characteristics table 9 . range +fs midscale ?fs lsb 10 v +10 v 0 v ?10 v +1220 v 5 v +5 v 0 v ?5 v +610 v 2.5 v +2.5 v 0 v ?2.5 v +305 v internal/external re feren ce the AD7617 can operate with either an internal or external reference. the devic e contains an on - chip 2.5 v band gap refer - ence. the refinout pin allows access to the 2.5 v reference that generates the on - ch ip 4.096 v reference internally, or it allows an external reference of 2.5 v to be applied to the AD7617 . an externally applied reference of 2.5 v is also amplified to 4.0 96 v using the internal buffer. this 4.096 v buffered reference is the reference used by the sar adc. the refsel pin is a logic input pin that allows the u ser to select between the in ternal reference and an external reference. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled , and an external reference voltage must be applied to the refinout pin. the internal reference buffer is always enabled. after a full reset , the AD7617 operates in the r eference mode selected by the ref sel pin. decoupling is required on the refinout pin for both the internal and external reference options. a 100 nf , x7 r ceramic capacitor is required on the refinout pin to refinoutgnd. 1m? clamp vxx 1m? clamp vxxgnd r fb r fb c r r analog input signal AD7617 16077-008 ?30 ?25 ?20 ?15 ?10 ?5 0 5 100 1k 10k 100k a ttenu a tion (db) input frequenc y (hz) 10v range 5v range 2.5v range 16077-244 0 1 2 3 4 5 6 100 1k 10k 100k ph a se ( s ) i n pu t f r eq u en c y ( hz) 10v range 5v range 2.5v range 16077-246 011. . . 111 011. . . 110 000. . . 001 000. . . 000 111. . . 111 100. . . 010 100. . . 001 100. . . 000 ? f s + 1 / 2 l s b 0 v ? 1 / 2 l s b + f s ? 3 / 2 l s b a dc c o d e ana l og in pu t + f s ? (? f s) 2 n * *where n is the number of bits of the converter l s b = 16077-009
data sheet AD7617 rev. 0 | page 25 of 51 the AD7617 contains a reference buffer configured to amplify the reference voltage to ~4.096 v. a 10 f , x5r ceramic capacitor is required bet ween refcap and refgnd. the reference voltage available at the refinout pin is 2.5 v. when the AD7617 is configured in external referenc e mode, the refinout pin is a high input impedance pin. if the internal reference is applied elsewhere within the system , i t must first be buffered externally. figure 48 . reference circuitry shut d own m ode the AD7617 enter s shutdown m ode by keeping the reset pin low for greater than 1.2 s. when the reset pin is set from low to high , the device exit s shutdown mode and enter s normal mode. when the AD7617 is placed in shutdown mode, the current c onsumption is typically 48 a , and the power - up time to perform a write to the device is approximately 24 0 s . power - up time to perform a conversion is 15 ms. in shut down mode , all circuitry is powered down and all registers are cleared and reset to their default values. digital filter the AD7617 contains an optional digital first - order sinc filter for use in applications where slower throughput rates are in use or wher e higher snr or dynamic range is desirable. the osr of the digital filter is controlled in hardware using the oversampling pins, os 2 to os 0 (osx) , or in software via the os bits within the c onfiguration r egister . in software mode, oversampling is enabled for all channels after the os bits are set in the c onfiguration r egister . in hardware mode, the osx signals at the time a full reset is released determine the osr used. table 10 provides the oversampling bit decoding to select the different oversample rates. in addition to the oversampling function, the output result is decimated to 14 - bit resolution. if the os x pins / os bits are set to select an os ratio of eight, the next convst rising edge takes the first sample for the selected channel, and the remaining seven samples for that chan nel are taken with an internally generated sampling signal. these samples are then averaged to yield an improvement in snr performance. as the os ratio increases, the ?3 db frequency is reduced, and the allowed sampling frequency is also reduced. t he conversion time extends as the oversampling rate is increased, and the busy signal scales with oversampling rates. acquisition and conversion time increase linearly with oversampling ratio. if oversampling is enabled with the sequencer , or in burst mode, the extra samples are gathered for a given channel before the sequencer moves on to the next channel. table 10 shows the typical snr performance of the device for each permissible oversampling rati o. the input tone used was a 1 k hz sine wave for the three input ranges of the device. a plot of snr vs. osr is shown in figure 49. figure 49 . typical snr vs. osr for all analog input ranges table 10 . oversampling bit decoding osx pins/ os b its os r typical snr (db) ? 3 db b andwidth (khz) 2.5 v range 5 v range 10 v range all ranges 000 no oversampling 83.8 84.6 84.9 37 001 2 84.2 85.0 85.3 36.5 0 10 4 84.5 85.2 85 .5 35 0 11 8 84.9 85.5 85.7 30.5 100 16 85.2 85.6 85.8 22 101 32 85.4 85.7 85.8 13.2 110 64 85.4 85.6 85.6 7.2 111 128 84.7 85.1 85.2 3.6 buf 2.5v ref refinout refsel refinoutgnd refinoutgnd refcap 100nf 10f 16077-010 83.0 83.5 84.0 84.5 85.0 85.5 86.0 86.5 87.0 0 10 20 30 40 50 60 snr (db) osr f in = 1khz 2.5v range 5v range 10v range 16077-0 1 1
AD7617 data sheet rev. 0 | page 26 of 51 applications informa tion functionality overvi ew the AD7617 has two main modes of operation : hardware mode and software mode . additionally , the communication s interface for hardware or software mode can be serial or parallel. depending on the mode of operation and interface chosen, certain functional - ity may not be available. full functionality is available in both software serial and software parallel mode with restricted functionality in hardware serial mode and hardware parallel mode. table 11 shows the functionality available in the different modes of operation. power supplies the AD7617 has two independent power supplies, v cc and v drive , t hat supply the analog circuitry and digital interface , respectively. decouple both t he v cc supply and the v drive supply with a 10 f capacitor in parallel with a 100 nf capacitor. additionally , these supplies are regulated by two internal ldo regulators. the analog ldo (aldo) typically supplies 1.8 7 v . decouple the aldo with a 10 f capacitor between the regcap an d reg gnd pins. the digital ldo (dldo) typically supplies 1.89 v . decouple the dldo with a 10 f capacitor between the regcapd and reggnd d pins. the AD7617 is robust to power supply sequencing. the recom - mended sequence is to power up v drive first , followed by v cc . hold reset low until both supplies are stabilized. typical connections figure 50 shows the typical connections required for correct operation of the AD7617 . decouple t he v cc and v drive supplies as shown in figure 50 . place t he smaller, 0.1 f capacitor as close to the supply pin as possible , with the larger 10 f bulk capacitor in parallel. decouple t he reference and ldo regulators as shown in figure 50 and as described in table 7 . the analog input pins require a matched resistance, r, o n both the vxa and vxagnd (similarly , vxb and vxbgnd) inputs to avoid a gain error on the analog input channels caused by an impedance mismatch. table 11 . functionality matrix functionality operation mode 1 software mode , hw_rngselx = 00 hardware mode , hw_rngselx 00 serial , ser/ par = 1 parallel , ser/ par = 0 serial , ser/ par = 1 parallel , ser/ par = 0 internal/external reference yes yes yes yes selectable analog input ranges individual channel configuration yes yes no no common channel configuration no no yes yes sequential sequencer yes yes yes yes fully configurable sequencer yes yes no no burst m ode yes yes yes yes on - c hip over s ampling yes yes yes no crc yes yes yes no diagnostic channel conversion yes yes no no hardware r eset yes yes yes yes serial 1 - wire mode yes no yes no serial 2 - wire mode yes no yes no register a ccess yes yes no no 1 yes means available; no means not available.
data sheet AD7617 rev. 0 | page 27 of 51 figure 50 . typical external connections 16077-300 adc adc pga pga buf 2.5v ref aldo dldo r r r r c c 10f x5r 0.1f x7r refinout refinoutgnd refcap refgnd v cc v drive 5v 2.5v/3.3v 10f 10f 0.1f 0.1f 10f 10f AD7617 regcap reggnd regcapd reggndd vxa vxagnd vxbgnd vxb mux mux
AD7617 data sheet rev. 0 | page 28 of 51 device configuration operational mode the mode of operation, hardware mode or software mode , is configured when the AD7617 is released from full reset . the logic level of the hw_rngselx pins when the reset pin t ransitions from low to hi gh determines the operational mode. the hw_rngselx pins are dual function. if hw_rngselx = 00 , the AD7617 enter s software mode. any othe r combination of the hw_rngselx configure s the AD7617 in hardware mode and the analog input range is configured as per table 8 . after software mode is configured , the logic level of the hw_rngselx si gnals is ignored. after an operation al m ode is configured , a full reset via the reset pin is required to exit the operation al mode and to set up an alternative mode. if hardware mode is selected , all further device configuration is via pin control. access to the on - chip registers is prohibited in hardware mo de. in software mode , the interface and reference configuration must be configured via pin control ; however, all further device configuration is via register access only . internal / external reference the internal reference is enabled or disabled when the AD7617 is released from a full reset . the logic level of the refsel signal when the reset pin transitions from low to h igh configures the reference. after the reference is configured , changes to the logic level of the r efsel signal are ignored. if the refsel signal is set to logic 1 , the i nternal reference is enabled. if refsel is set to l ogic 0 , the internal reference is disabled and an external reference must be supplied to the refinout pin for correct operation of the AD7617 . a full reset via the reset pin is required to exit the operation al mode and set up an alternative mode. connect a 100 nf capacitor between the refinout and refinoutgnd pins. if using an external reference, place a 10 k band limiting resistor in series between the reference and the refinout pin of the AD7617 . digital interface the digital interface selection, parallel or serial, is configured when the AD7617 is released from a full reset . the logic level of the ser/ pa r signal when the reset pin transitions from low to high configures the interface . if the ser/ pa r signal is set to 0 , the parallel interface is enabled. if the ser/ pa r signal is set to 1 , the serial interface is selected. additionally , if the serial interface is selected , the ser1w signal is monitored when the reset pin is released to determine if serial 1 - wire or 2 - wire mode is selec ted. after the interface is configured , changes to the logic level of the ser/ pa r signal or the ser1w signal ( when the serial interface is enabled ) are ignored. a full reset via the reset pin is required to exit the operation mode and set up an alternative mode. hardware mode if hardware mode is selected , the available functionality is restricted and all functionality is configured via pin control. the logic level of the following signals is checked after a full reset to configure the functionality of the AD7617 : crc, burst, seqen, and osx . table 12 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. after the device is configured , a full reset via th e reset pin is required to exit the configuration and set up an alternative configuration. functionality availability is restricted depending on the interface type select ed . see table 11 for a full list of the functionality available in hardware parallel or serial mode. the chselx pins are queried at reset to determine the initial a nalog input channel pair to acquire for conversion or to configure the initial settings for the sequencer. the channel pair selected for conversion or the hardware sequencer can be reconfigured during normal operation by setting and maintaining the chselx signal level before the convst rising edge until the busy falling edge. the hw_rngselx signals control the analog input range for all 16 analog input channels. a logic cha nge on these pins has an imme diate effect on the analog input range; however, the typ ical settling time is approximately 120 s, in addition to the normal acquisition time requirement. the recommended practice is to hardwire the range select pins according to the desired input range for the system signals. access to the on - chip registers i s prohibited in hardware mode.
data sheet AD7617 rev. 0 | page 29 of 51 table 12 . summary of l atched h ardware s ignals 1 signal latched at full reset read at reset read d uring busy edge driven hw mode sw mode hw mode sw mode hw mode sw mode hw mode sw mode refsel yes yes seqen yes no hw_rngselx (range change) yes yes yes no hw_rngselx (h ardware (hw) or software ( sw ) m ode) yes yes ser/ par yes yes crcen yes no osx yes no burst yes no chselx yes no yes no ser1w yes yes 1 blank cells in table 12 mean not applicable. software mode if software mode is selected and the reference and interface type is configured, all other configuration settings in the AD7617 are controlled via the on - chip registers. all functionality of the AD7617 is available when software mode is selected. table 12 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. r eset functionality the AD7617 has two reset modes: full or partial . the reset mode selected is dependent on the length of the reset low pulse. a partial reset requires the reset pin to be held low between 40 ns and 500 ns. after 50 n s from release of reset , the device is fully functional and a conversion can initiate . a full reset requires the reset pin to be held low for a minimum of 1.2 s. after 15 m s from release of reset , the devices is completely reconfigure d and a conversion can init i ate. a partial reset reinitializes the following modules: ? sequencer ? digital f ilter ? spi ? both sar adcs the current conversion result is discarded on completion of a partial reset. the partial reset does not affect the register values programmed in software mode or the latches that store the user configuration in both hardware and software modes. a dummy conversion is required in software mode after a partial reset. a full reset returns the device to its default power - on state. the following fe atures are configured when the AD7617 is released from full reset : ? hardware m ode or s oftwar e m ode ? internal/ e xternal r eference ? i nterface ty pe on power - up , the reset signal can be released as soon as both the v cc and v drive supplies are stable. t he logic level of the hw_rngselx , refsel, ser/ pa r and db4/ ser1w pins when the reset pin is released after a full reset determine s the configuration. if hardware mode is selected , the functionality determined by the crc, bursten, seqen , and osx signals is also latched when the reset pin transitions from low to high in full reset mode . after the functionality is configured, changes to these signals are ignored. in hardware mode, the analog input range ( hw_rngselx signals) can be configured during either a full or p artial reset or during normal operation ; however, hardware/ software mode selection requires a full reset to reconfigure while this setting is latched. in hardware mode , the chselx and hw_rngsel x pins are queried at release from both a full and a partial reset to perform the following actions: ? determine t he initial analog input channel pair to acquire for conversion . ? c onfigure the init ial settings for the sequencer . ? select the analog input voltage range . the chselx and hw_rngselx signals are not latched. the channel pair selected for conversion , or the hardware sequencer , can be reconfigured during normal operation by setting and maintaining the chselx signal level before the convst rising edge , and ensuring the signal level remains constant until after busy transitions low again. see the channel selection section for further details. in software mode , all additional functionality is con figured by controlling the on - chip registers.
AD7617 data sheet rev. 0 | page 30 of 51 pin function overvie w there are several dual function pins on the AD7617 . their functio nality is dependent on the mode of operation selected by the hw_rngselx pins. table 13 outlines the pin functionality in the different modes of operat ion and interface modes. figure 51 . AD7617 configuration at r eset table 13 . pin functionality overview pins operation mode software, hw_rngselx = 00 hardware, hw_rngselx 00 serial, ser/ par = 1 parallel, ser/ par = 0 serial, ser/ par = 1 parallel, ser/ par = 0 chselx no function, connect to dgnd no function, connect to dgnd chselx chselx sclk/ rd sclk rd sclk rd wr /burst connect to dgnd wr burst burst db15 /os0 to db 13/ os 2 connect to d gnd db 15 to db1 3 osx db15 to db 13 db12/sdoa sdoa db12 sdoa db12 db11/sdob sdob , l eave floating for s erial 1 - wire mode db 11 sdob db 11 db10/ sdi sdi db 10 connect to d gnd db 10 db9 to db6 , db3 to db 2 connect to d gnd db 9 to db 6 , db 3 to db 2 connect to d gnd db9 to db6, db3 to db 2 db5/crcen connect to d gnd db5 crcen db5 db4/ ser1w ser1w db4 ser1w db 4 db1 to db0 connect to dgnd db1 to db0 connect to dgnd float or pull to dgnd via a 10 k resistor hw_rngselx hw_rngselx, connect to dgnd hw_rngselx, connect to dgnd hw_rngselx, configure analog input range hw_rngselx, configure analog input range seqen no function, connect to dgnd no function, connect to dgnd seqen seqen refsel refsel refsel refsel refsel v cc v drive reset convst busy mode range setting in hw mode ch x y z acq x conv x acq y conv y t reset_wait t device_setup t reset_setup t reset_hold all modes hardware mode only refsel ser/par, ser1w hw_rngsel0, hw_rngsel1 crcen, burst seqen, os0 to os2 chsel0 to chsel2 action 16077-012
data sheet AD7617 rev. 0 | page 31 of 51 digital interface channel selection hardware mode the logic level of the chselx signals determine the channel pair for conversion; s ee table 14 for signal decoding information. the chselx signals at the time that either full or partial reset is released determine the initial channel pair to sample. after a reset , t he logic levels of the chselx signals are examined during the busy high period to set the channel pair for the next conversion. the chselx signal level m ust be set before convst goes from low to high and be maintained until busy goes from high to low to indicate a conversion is complete. see figure 52 for further details. software mode in software mode , the channels for conversion are selected by control of the c hannel r egister . on power - up or after a reset , the default channels selected for conversion are channel v 0 a and channel v0 b (see figure 53) . table 14. chselx pin decoding channel selection input pin analog input channels for conversion ch sel 0 ch sel 1 ch sel 2 0 0 0 v 0 a , v0 b 0 0 1 v1 a , v1 b 0 1 0 v2 a , v2 b 0 1 1 v3 a , v3 b 1 0 0 v4 a , v4 b 1 0 1 v5 a , v5 b 1 1 0 v6 a , v6 b 1 1 1 v7 a , v7 b figure 52 . hardware mode channel conversion setting figure 53 . software serial mode channel conversion setting reset convst busy ch x a/b x a/b y a/b z ch y ch z ch... chsel2 to chsel0 data bus configure point configure point configure point initial setup 16077-013 reset convst busy cs write ch x write ch y write ch z write ch ... sdi a/b 0 a/b x a/b y sdoa, sdob chx conversion start do not care 16077-014
AD7617 data sheet rev. 0 | page 32 of 51 figure 54. software parallel mo de channel conversion setting parallel interface the parallel interface reads the conversion results, and config- ures and reads back the on-chip registers. data can be read from the AD7617 via the parallel data bus with standard cs , rd , and wr signals. to read the data over the parallel bus, tie the ser/ par pin low. reading conversion results the convst signal initiates the conversion process. a low to high transition on the convst signal initiates a conversion of the selected inputs. the busy signal goes high to indicate a conversion is in progress. when the busy signal transitions from high to low to indicate that a conversion is complete, it is possible to read back conversion results on the parallel interface. data can be read from the AD7617 via the parallel data bus with standard cs and rd signals. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines, db15 to db2, leave their high impedance state when both cs and rd are logic low. db15 is the msb of the conversion result and db2 is the lsb of the 14-bit conversion result. the data lines db1 and db0 are only used for register write/read operations or for reading the crc result. the rising edge of the cs input signal three-states the bus, and the falling edge of the cs input signal takes the bus out of the high impedance state. cs is the control signal that enables the data lines; it is the function that allows multiple AD7617 devices to share the same parallel data bus. the number of required read operations depends on the device configuration. a minimum of two reads are required to read the conversion result for the simultaneously sampled a and b channels. if additional functions such as crc, status, and burst mode are enabled, the number of required readbacks increases accordingly. the rd pin reads data from the output conversion results register. applying a sequence of rd pulses to the rd pin of the AD7617 clocks the conversion results out from each channel onto the parallel bus, db15 to db2. the first rd falling edge after busy goes low clocks out the conversion result from channel a x . the next rd falling edge updates the bus with the channel b x conversion result. writing register data in software mode, all the read/write registers in the AD7617 may be written to over the parallel interface. a register write command is performed by a single 16-bit parallel access via the parallel bus (db15 to db0), cs , and wr signals. provide data written to the AD7617 on the db15 to db0 inputs, with db0 being the lsb of the data-word. the format for a write command is shown in figure 55. bit d15 must be set to 1 to select a write command. bits[d14:d9] contain the register address. the subsequent nine bits (bits[d8:d0]) contain the data to be written to the selected register. see the register summary section for the complete list of register addresses. data is latched into the device on the rising edge of wr . figure 55. parallel interface register write reading register data all the registers in the device can be read over the parallel interface. a register read is performed by first writing the address of the register to be read to the AD7617. the format for a register read command is shown in figure 57. bit d15 must be set to 0 to select a read command. bits[d14:d9] contain the register address. the subsequent nine bits (bits[ d8:d0]) are ignored. the read command is latched into the AD7617 on the rising edge of wr . this latch transfers the relevant register data to the output register. the register data can then be read on the db15 to db0 pins by using a standard read command. see figure 57 for additional information. reset convst busy cs wr rd ch x a 0 b 0 ch y a x b x ch z a y b y ch db0 to db15 chx conversion start 16077-153 cs wr write reg 1 write reg 2 db15 to db0 16077-020
data sheet AD7617 rev. 0 | page 33 of 51 figure 56. parallel interface conversion readback figure 57. parallel interface register read serial interface to interface to the AD7617 over the spi, the ser/ par pin must be tied high. the cs and sclk signals transfer data from the AD7617. the AD7617 has two serial data output pins, sdoa and sdob. data is read back from the AD7617 using serial 1-wire or serial 2-wire mode. in serial 2-wire mode for the AD7617, conversion results from channel v0a to channel v7a appear on sdoa, and conversion results from channel v0b to channel v7b appear on sdob. in serial 1-wire mode, conversion results from channel v0b to channel v7b are interlaced with conversion results from channel v0a to channel v7a. to achieve the maximum throughput, it is required to use 2-wire mode. to read back data over both sdoa and sdob, the ser1w pin must be tied high. if data is read back over sdoa only, the tie ser1w pin low. serial 1-wire or 2-wire mode is configured when the AD7617 is released from full reset. reading conversion results the convst signal initiates the conversion process. a low to high transition on the convst signal initiates a conversion of the selected inputs. the busy signal goes high to indicate a conversion is in progress. when the busy signal transitions from high to low to indicate that a conversion is complete, it is possible to read back conversion results on the serial interface. the cs falling edge takes the data output lines, sdoa and sdob, out of three-state and clocks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the serial data outputs, sdoa and sdob. figure 58 shows a read of two simultaneous conversion results using two sdox lines on the AD7617. if the status register is appended to the conversion results or operating in sequencer burst mode where multiples of 16 sclk transfers access data from the AD7617, hold cs low to frame the entire data. data can also be clocked out using just one sdox line, in which case, use sdoa to access all conversion data. for the AD7617 to access both channel vxa and channel vxb conversion results on one sdox line, a total of 32 sclk cycles is required. frame these 32 sclk cycles using one cs signal, or individually frame each group of 16 sclk cycles using the cs signal. the disadvantage of using just one sdox line is that the throughput rate is reduced. in serial 2-wire, 16 sclk cycles are required to read a conversion result. the first sclk cycle reads the msb of the conversion results. the 14 th sclk cycle reads the lsb. the last two sclk cycles clock out zeros, as shown in figure 58. in serial 1-wire, 32 sclk cycles (or 2 16 sclk cycles) are required to read a conversion result. the first 16 sclk cycles read the 14-bit channel vxa result, followed by two zeros. the next 16 sclk cycles read the 14-bit channel vxb result, followed by two zeros, as shown in figure 59. with crc enabled, all 16 sclk cycles read the status register. refer to the crc section for further information. leave the unused sdob line unconnected in serial 1-wire mode. if using sdoa as a single serial data output line, the channel results are output in the following order: vxa and vxb. figure 59 shows a 1-wire, serial readback operation. the speed at which the data can be read back in serial interface mode is dependent on spi frequency, v drive supply, and the capacitance of the load on the sdo line, c load . table 15 shows a summary of the maximum speed achievable for various conditions. table 15. spi frequency vs. load capacitance and v drive v drive (v) c load (pf) spi frequency (mhz) 2.3 to 3 20 40 3 to 3.6 30 50 convst busy cs rd conv a conv b db15 to db0 16077-016 cs wr rd read reg 1 data reg 1 read reg 2 data reg 2 db15 to db0 16077-023
AD7617 data sheet rev. 0 | page 34 of 51 figure 58. serial interface, 2-wire mode reading conversion result figure 59. serial interface, 1-wire mode reading conversion result 16077-017 convst busy cs 1 2 3 14 15 16 sclk 15(msb) 14 13 2(lsb) sdoa 15(msb) 14 13 2(lsb) sdob channel vax result channel vbx result 1 6077-018 convst busy cs 1 2 15 16 17 18 31 32 sclk db 15(msb) db 2(lsb) zero zero db 15(msb) db 2(lsb) zero zero sdoa channel vax result channel vbx result
data sheet AD7617 rev. 0 | page 35 of 51 writing register data all the read/write registers in the AD7617 can be written to over the serial interface. a register write command is performed by a single 16 - bit spi access. the format for a write command is shown in table 16 . bit d15 must be set to 1 to select a write command. bits[d14:d9] contain the register address. the subsequent nine bits (bits[d8:d0]) contain the data to be written to the selected register. figure 60 shows a typical serial interface register write command. reading register data all the registers in the device can be read over the serial interface. a register read is performed by issuing a register read command followed by an additional spi command that can be either a valid command or no operation ( nop ) . the format for a read command is shown in table 17 . bit d15 must be set to 0 to select a read command. bits[d14:d9] contain the register address. the subsequent nine bits (bits[d8:d0]) are ignored. see the r egist er summary section for the complete list of register addresses. figure 61 shows a typical serial interface register read command. figure 60 . serial interface register write figure 61 . serial interface register read table 16 . write command message configuration msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 w / r regaddr[5:0] data[8:0] 1 register address data to write table 17 . read command message configuration msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 w / r regaddr[5:0] data[8:0] 0 register address do not care convst cs write reg 1 write reg 2 write reg 3 sdi conv result invalid invalid sdoa, sdob 16077-021 convst cs read reg 1 read reg 2 read reg 3 sdi conv result reg 1 data reg 2 data sdoa 16077-024
AD7617 data sheet rev. 0 | page 36 of 51 sequencer the AD7617 features a highly configurable on - chip sequencer. the functionality and configuration of the sequencer is dependent on the mode of operation of the AD7617 . in h ardware m ode , the sequencer is sequential only . the sequencer always start s converting at c hannel v 0 a and channel v 0 b and convert s each subsequent channel up to the configured end channel. in s oftware m ode , the sequencer has additional functionality and configurability . the sequencer stack has 32 uniquely configurable sequence steps , allowing any channel order to be programmed . additionally , any channel vx a input can be paired with any channel vx b input or diagnostic channel. the sequencer c an be operated with or without the b urst function enabled. with the burst function enabled , only one convst pulse is required to convert every channel in a sequence. with burst mode disabled , one convst pulse is required for every conversio n step in the sequence. see the burst sequencer section for additional details on operating in burst mode. hardw are mode sequencer in h ardware m ode , the sequencer is controlled by the seqen pin and the chselx pins. the sequencer is enabled or disabled when the AD7617 is released from full reset . the logic level of the seqen pin when the reset pin is released determines whether the sequencer is enabled or disabled ( see table 18 for settings ) . after the reset pin is released , the function is fixed and a full reset via the reset pin is required to exit the function and set up an alt ernative configuration . table 18 . hardware mode sequencer configuration seqen interface mode 0 sequencer disabled 1 sequencer enabled when t he sequencer is enabled , the logic levels of the chselx pins determine the channels selected for conversion in the sequence. the chselx pins at the time reset is release d determine the initial settings for the channels to convert in the sequence. to reconfigure the channels selected for conve rsion thereafter , set the chselx pins to the required setting for the duration of the final busy pulse before the current conversion sequence is complete. see figure 62 for further details. table 19. chsel x pin decoding sequencer channel selection input pin analog input channels for sequential conversion ch sel 0 ch sel 1 ch sel 2 0 0 0 v0 x only 0 0 1 v0 x to v1 x 0 1 0 v0 x to v2 x 0 1 1 v0 x to v3 x 1 0 0 v0 x to v4 x 1 0 1 v0 x to v5 x 1 1 0 v0 x to v6 x 1 1 1 v0 x to v7 x software mode sequen cer in software mode, the AD7617 contains a 32 - layer fully configurable sequencer stack. control of the sequencer is achieved by programming the configuration register and sequencer stack registers via the parallel or serial interface. each stack step can be individually programmed to p air any input from channel vxa to any input from channel vxb , or any diagnostic channel can be selected for conversion. the sequencer depth can be set to any length from 1 to 32 layers . the sequencer depth is controlled via the ssrenx bit. set the ssrenx b it in the sequencer stack register corresponding to the last step required. the channels to convert are selected by programming the aselx and bselx bits in each sequence stack register for the depth required. the sequencer is activated by setting the seqen bit in the configuration register to 1. figure 62 . hardware mode sequencer configuration reset seqen convst busy ch x ch y ch z chsel2 to chsel0 a/b 0 a/b x a/b 0 a/b y a/b 0 data initial setup configure point configure point a/b x-1 a/b y-1 16077-025
data sheet AD7617 rev. 0 | page 37 of 51 to configure and enable the sequencer , it is recommended to complete the followin g procedure (see figure 63) : 1. configure the analog input range for the required analog input channels . 2. program the sequencer stack registers to select the channels for the sequence . 3. set the ssr en x bit in the last requir ed sequence step . 4. set the seqen bit in the configuration register . 5. provide a dummy convst pulse . 6. cycle through convst pulses and conversion reads to step through each element of the sequencer stack . the sequence automatically restarts from the first elemen t in the sequencer stack with the next convst pulse . following a partial reset, the sequencer pointer is repositioned to the first layer of the stack, but the register programmed values remain unchanged. burst sequencer burst mode avoids generating a convst pulse for each step in a sequence of conversions. one convst pulse converts every step in the sequence. the burst sequencer is an additional feature that works in conjunction with the sequencer. if the burst function is enabled, one co nvst pulse initiates a conversion of all the channels configured in the sequencer. the burst function avoids generating a convst pulse for each step in a sequence of conversions , as is the case when the burst function is disabled. configuration of the burs t function varies depending on the mode of operation: hardware or software mode. see the hardware mode burst section and the software mode burst section for specific details on configuring the burst function in the each mode. when configured, the burst sequence is initiated at the rising edge of con vst. the busy pin goes high to indicate that a conversion is in progress. the busy pin remain highs until all conversions in the sequence are complete. the conversion results are available for read back after the busy pin goes low. the number of data reads required to read all the data in the burst sequence is dependent on the length of the sequence configured. the conversion results are presented on the data bus (parallel or serial) in the same order as the programmed sequence. the t hroughput rate of the AD7617 is limited in burst mode and dependent on the length of the sequence. each channel pair requires an acquisition, conversion , and readback time. the time taken to complete a sequence with number of channel pairs, n, is estimated by t burst = ( t conv + 25 ns) + ( n C 1)( t acq + t conv ) + n ( t rb ) w here : t conv is the typical conversion time . t acq is typical acquisition time. t rb is the time required to read back the conversion results in either serial 1 - wire, serial 2 - wire , or parallel mode . hardware mode burst burst mode is enabled in hardware mode by setting the burst pi n to 1. the seqen pin must also be set to 1 to enable the sequencer. in hardware mode, the burst sequencer is controlled by the burst, seqen, and chselx pins. the burst sequencer is enabled or disabled when the AD7617 is released from full reset. the lo gic level of the seqen pin and the burst pin when the reset pin is released determines whether the burst sequencer is enabled or disabled. after the reset pin is released, the function is fixed and a full reset via the reset pin is required to exit the function and set up an alternative configuration. when the burst sequencer is enabled, the logic levels of the chselx pins determine the channels selected for conversion in the burst sequence. the chselx pins at the time reset is released determines the initial settings for the channels to convert in the burst sequence. to reconfigure the channels selected for conver - sion after a reset , set the chselx pins to the required setting for the duration of the next busy pulse (see figure 64 for further details). software mode burst in software mode, the burst function is enabled by setting th e burst bit in the configuration register to 1. this action must be performed when setting the seqen bit in the configuration register as outlined in the steps described in the software mode sequencer section to configure the sequencer (see figure 65 for additional information). figure 63 . software mode sequencer configuration reset convst busy register setup a/b 0 s 0 1 s n ? 1 s n 0 data initial setup sequence start dummy conversion 16077-026
AD7617 data sheet rev. 0 | page 38 of 51 figure 64. burst sequencer, hardware mode figure 65. burst sequencer, software mode reset seqen burst c onvst busy ch x ch y ch z ch z ch z chsel2 to chsel0 a/b 0 a/b x?1 a/b x a/b 0 a/b y?1 a/b y a/b 0 a/b z?1 a/b z data configure point configure point configure point initial setup 16077-027 reset convst busy registe r setup a/b 0 s 0 s 1 s n?1 s n s 0 s 1 s n?1 s n data dummy conversion 16077-028
AD7617 data sheet rev. 0 | page 39 of 51 diagnostics diagnostic channels in addition to the 16 analog inputs, vxa and vxb, the AD7617 can also convert the following diagnostic channels: v cc and the aldo voltage. the diagnostic channels are selected for conversion by programming the channel register (see the channel register section) to the corresponding channel identifier. diagnos- tic channels can also be added to the sequencer stack in software mode but only provide an accurate reading at throughput rates <250 ksps. see figure 66 for a plot of the deviation from expected value vs. sampling frequency that can be expected when using the diagnostic channels. the expected output for each channel is governed by the following transfer functions: ?? ?? ref ref cc cc v vv code v ? ? ? ? 5 768 , 32 C4 ???? ?? ref ref aldo v v v code ldo ? ?? ? ? 10 768,32 7C 10 figure 66. deviation from expected value vs. sampling frequency figure 67. v cc diagnostic transfer function figure 68. aldo diagnost ic transfer function interface self test it is possible to test the integrity of the digital interface by selecting the communication self test channel in the channel register (see the channel register section). selecting the communication self test for conversion forces the conversion result register to a known fixed output. when conversion code is read, code 0x2aaa is output as the conversion code of adc a, and code 0x1555 is output as the conversion code of adc b. crc the AD7617 has a cyclic redundancy check (crc) checksum mode to improve interface robustness by detecting errors in data. the crc feature is available in both software (serial and parallel) mode and hardware (serial only) mode. the crc feature is not available in hardware parallel mode. the crc result is contained within the status register. enabling the crc feature enables the status register and vice versa. in hardware mode, the crcen pin controls the crc feature. the crc feature is enabled or disabled when the AD7617 is released from full reset. the logic level of the crcen pin when the reset pin is released determines whether the crc feature is enabled or disabled. set the crcen pin to 1 to enable the crc feature. after the reset pin is released, the function is fixed and a full reset via the reset pin is required to exit the function and set up an alternative configuration. see the reset functionality section for additional information. after being enabled, the crc result is appended to the conversion result and consists of a 16-bit word, where the first eight bits contain the channel id of the last channel pair converted and the last eight bits are the crc result. the result is accessed via an extra read command, as shown in figure 69. in software mode, the crc function is enabled by setting either the crcen bit or the statusen bit in the configuration register to 1 (see the status register section). 750 ?750 ?500 ?250 0 250 500 0600 500 400 300 200 100 sampling frequency (ksps) deviation from expected value (codes) aldo error v cc error 16077-035 29000 22000 23000 24500 26000 28000 25000 27000 4.50 4.75 5.00 5.50 5.25 expected output (codes) v cc (v) 16077-029 ?9000 ?8800 ?8600 ?8400 ?8200 ?8000 ?7800 ?7600 ?7400 ? 7200 1.75 1.80 1.85 1.90 1.95 expected output (codes) aldo (v) 16077-030
AD7617 data sheet rev. 0 | page 40 of 51 if the crc function is enabled, a crc is calculated on the conversion results for c han nel vx a and c hannel vx b . the crc is calculated and transferred on the serial or parallel interface after the con version results are transmitted, depending on the configuration of the device. the hamming d istance varies relative to the number of bits in the conversion result. for conversions with 119 bits , the hamming d istance is 4. for >119 bits , the hamming d istance is 1, that is, 1 - bit errors are always detected. the crc polynomial in use on the AD7617 is x 8 + x 2 + x + 1 the following is a pseudocode description of how the crc is implemented in the AD7617 : crc = 8?b0; i = 0; x = number of conversion channel pairs; for (i=0, iAD7617 is a n 8 - bit word equal to zero. the xor operation described in the preceding code is executed to calculate each bit of the c rc word for t he conversion result , a n . this crc word (crc1) is then used as the starting point for calculating the crc word (crc) for the conversion result, b n . the process repeats cyclically for each channel pair converted. depending on the mode of operation of the AD7617 , the status register value is appended to the conversion data and read out via an extra read command over the serial or parallel interface. the user can then repeat the xor calculation descri bed in the preceding code for the received conversion results to check whether both crc words match. see figure 69 f or a description of how the crc word is appended to the data for each mode of operation. figure 69 . crc readback for all modes convst busy a x b x crc ab(x) data a x b x a z b z crc ab(x:z) data a x crc ab(x) sdoa b x crc ab(x) sdob a x a z crc ab(x:z) sdoa b x b z crc ab(x:z) sdob parallel/serial (1-wire), sequencer/manual mode parallel/serial (1-wire), burst serial (2-wire), sequencer/manual mode serial (2-wire), burst 16077-032
data sheet AD7617 rev. 0 | page 41 of 51 r egist er summary the AD7617 has six read/write registers used for configuring the device in software mode and an additional 32 sequencer stack registers for programming the flexible on - chip sequencer and a read only status register. table 20 shows an overview of the read/w rite registers available on the AD7617 . the status register is an additional read only register than contains information on the channel pair previously converted and the crc result. table 20 . register summary 1 reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r / w 0x02 configuration r egister [15:8] addressing reserved 0x0000 r/w [7:0] sdef bursten seqen os statusen crcen 0x03 channel r egister [15:8] addressing reserved 0x0000 r/w [7:0] chb cha 0x04 input rangeregister a1 [15:8] addressing reserved 0x00ff r/w [7:0] v3 a v2 a v1 a v0 a 0x05 input range register a2 [15:8] addressing reserved 0x00ff r/w [7:0] v7 a v6 a v5 a v4 a 0x06 input range register b1 [15:8] addressing reserved 0x00ff r/w [7:0] v3 b v2 b vb1 v0 b 0x07 input range register b2 [15:8] addressing reserved 0x00ff r/w [7:0] v7 b v6 b vb5 v4 b 0x20 to 0x3f sequencer stack registers 0 to sequencer stack register 31 [15:8] addressing ssren 0 to ssren31 0x0000 2 r/w [7:0] bsel 0 to bsel31 asel 0 to asel31 n/a status r egister [15:8] a[3:0] b[3:0] n/a r [7:0] crc[7:0] 1 n/a means not applicable. 2 after a full or partial rest is issued, the sequencer stack register is reinitialized to cycle through channel v0 a and channel v0 b to channel v7 a and channel v 7 b . the remaining 24 layers of the stack are reinitialized to 0x0.
AD7617 data sheet rev. 0 | page 42 of 51 addressing register s the seven msbs written to the device are decoded to determine which register is addressed. the seven msbs consist of the register address (regaddr) , b its[5:0] , and the read/write bit. the register address bits determine which on - chip register is selected. the read/write bit determines if the remaining nine bits of data on the db10/ sdi lines are loaded into the addressed register. if the read/write bit is 1 , the bits load into the reg i ster addressed by the register select bits. if the read/wri te bit is 0 , th e command is seen as a read request. the addressed register data is available to be read during the next read operation. msb lsb d15 d14 d13 to d9 d8 to d0 w/ r regaddr , bit 5 regaddr , bits[4:0] data , bits [8:0] table 21. bit descriptions for the addressing registers bit s mnemonic description d15 w / r if a 1 is written to this bit , b its[ d 8: d 0] of this register are written to the register specified by regaddr , bits [5:0]. alternatively, if a 0 is written , the next operation is a read from the designated register. d14 regaddr , bit 5 if a 1 is written to this bit, the contents of regaddr , bits [4:0] specifies the 32 sequencer stack r egisters. alternatively , i f a 0 is written to this bit, a register is selected as defined by regaddr , bits [4:0] . [ d13 : d9 ] regaddr , bits [4:0] when w/ r = 1, the contents of regaddr , bits [4:0] determine re gister for selection as follows : 00001 : r eserved . 00010 : s elects the c onfiguration r egister . 00011 : s elects the c hannel r egister . 00100 : s elects input range register a1 . 00101 : s elects input range register a2 . 00110 : s elects input range register b1 . 00111 : s elects input range register b2 . 01000 : s elects the s tatus r egister when w/ r = 0 and regaddr , bits [4:0] contains 00000, the conversion codes are read . [d8: d0 ] data , bits [8:0] these bits are written into the corresponding register specified by regaddr , bits [5:0] . see the following sections for detailed descriptions of each register.
data sheet AD7617 rev. 0 | page 43 of 51 configuration register the configuration register is used in software mode to configure many of the main functions of the adc, including the sequencer , burst mode, oversampling, and crc options. address: 0x02, reset: 0x0000, name: configuration register table 22. bit descriptions for the configuration register bits bit name settings description reset 1 access [15:9] addressing 0 bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 rw 8 reserved reserved. 0x0 r/w 7 sdef self detector error flag. n/a r 0 test passed. the AD7617 has configured itself successfully after power-up. 1 test failed. an issue was detected during device configuration. a reset is required. 6 bursten burst mode enable. 0x0 rw 0 burst mode is disabled. each channel pair to be converted requires a cnvst pulse. 1 a single cnvst pulse converts every ch annel pair programmed in the 32-layer sequencer stack registers up to and including the layer defined by the ssrenx bit. see the software mode sequencer section and the software mode burst section for further details. 5 seqen channel sequencer enable. 0x0 rw 0 the channel sequencer is disabled. 1 the channel sequencer is enabled. [4:2] os oversampling (os) ratio, samples per channel. 0x0 rw 000 oversampling disabled. osr = 1. 001 oversampling enabled, osr = 2. 010 oversampling enabled, osr = 4. 011 oversampling enabled, osr = 8. 100 oversampling enabled, osr = 16. 101 oversampling enabled, osr = 32. 110 oversampling enabled, osr = 64. 111 oversampling enabled, osr = 128. 1 statusen status regist er output enable. 0x0 rw 0 the status register is not read out when reading the conversion result. 1 the status register is read out at the end of all the conversion words (including the self test channel if enabled in sequencer mode) if all the selected channels are read out. the crc result is included in the last eight bits. 0 crcen crc enable. the statusen and crcen bits have identical functionality. 0x0 rw 1 n/a means not applicable. crc enable status register output enable self detector error flag os ratio, samples per channel 111: osr=128. 110: osr=64. 101: osr=32. 100: osr=16. 011: osr=8. 010: osr=4. 001: osr=2. 000: osr=1. burst mode enable channel sequencer enable 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [0] crcen (r/w ) [8] reserved [1] statusen (r/w ) [7] sdef (r) [4:2] os (r/w) [6] bursten (r/w ) [5] seqen (r/w)
AD7617 data sheet rev. 0 | page 44 of 51 channel register address: 0x03, reset: 0x0000, name: channel register in software manual mode, the channel register selects the input channel or self test channel for the next conversion. table 23. bit descriptions for the channel register bits bit name settings description reset access [15:9] addressing bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved. 0x0 r/w [7:4] chb channel selection bits for adc b channels. 0x0 r/w 0000 v0b. 0001 v1b. 0010 v2b. 0011 v3b. 0100 v4b. 0101 v5b. 0110 v6b. 0111 v7b. 1000 v cc . 1001 aldo. 1010 reserved. 1011 set the dedicated bits for digital interfac e communication self test function. when conversion codes are read, code 0x2aaa is read out as the conversion code of channel a, and code 0x1555 is output as the conversion code of channel b. 1100 reserved. [3:0] cha channel selection bits for adc a channe ls. settings are the same as for adc b. 0x0 r/w channel selection bits for adc a channels 1100: reserved. 1011: 0x2aaa. 1010: reserved. ... 10: v2a. 1: v1a. 0: v0a. channel selection bits for adc b channels 1100: reserved. 1011: 0x1555. 1010: reserved. ... 10: v2b. 1: v1b. 0: v0b. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w) [3:0] cha (r/w) [8] reserved [7:4] chb (r/w)
data sheet AD7617 rev. 0 | page 45 of 51 input range registers input range register a1 and input range register a2 select from one of the three possible input ranges (10 v, 5 v, or 2.5 v) for analog input channel v0a to channel v7a. input range register b1 and input range register b2 select from one of the three possi ble input ranges (10 v, 5 v, or 2.5 v) for analog input channel v0b to channel v7b. input range register a1 address: 0x04, reset: 0x00ff, name: input range register a1 table 24. bit descriptions for input range register a1 bits bit name settings description reset access [15:9] addressing bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved. 0x0 r/w [7:6] v3a v3a voltage range selection. 0x3 r/w 00 v3a 10 v. 01 v3a 2.5 v. 10 v3a 5 v. 11 v3a 10 v. [5:4] v2a v2a voltage range selection. 0x3 r/w 00 v2a 10 v. 01 v2a 2.5 v. 10 v2a 5 v. 11 v2a 10 v. [3:2] v1a v1a voltage range selection. 0x3 r/w 00 v1a 10 v. 01 v1a 2.5 v. 10 v1a 5 v. 11 v1a 10 v. [1:0] v0a v0a voltage range selection. 0x3 r/w 00 v0a 10 v. 01 v0a 2.5 v. 10 v0a 5 v. 11 v0a 10 v. v0 a vo l ta g e r a n g e se l e cti o n 11: v0a = +/-10v. 10: v0a = +/-5v. 01: v0a = +/-2.5v. 00: v0a = +/-10v. v1 a vo l ta g e r a n g e se l e cti o n 11: v1a = +/-10v. 10: v1a = +/-5v. 01: v1a = +/-2.5v. 00: v1a = +/-10v. v3 a vo l ta g e r a n g e se l e cti o n 11: v3a = +/-10v. 10: v3a = +/-5v. 01: v3a = +/-2.5v. 00: v3a = +/-10v. v2 a vo l ta g e r a n g e se l e cti o n 11: v2a = +/-10v. 10: v2a = +/-5v. 01: v2a = +/-2.5v. 00: v2a = +/-10v. 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [1:0] v0a (r/w ) [8] reserved [3:2] v1a (r/w) [7:6] v3a (r/w) [5:4] v2a (r/w)
AD7617 data sheet rev. 0 | page 46 of 51 input range register a2 address: 0x05, reset: 0x00ff, name: input range register a2 table 25. bit descriptions for input range register a2 bits bit name settings description reset access [15:9] addressing bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved. 0x0 r/w [7:6] v7a v7a voltage range selection. 0x3 r/w 00 v7a 10 v. 01 v7a 2.5 v. 10 v7a 5 v. 11 v7a 10 v. [5:4] v6a v6a voltage range selection. 0x3 r/w 00 v6a 10 v. 01 v6a 2.5 v. 10 v6a 5 v. 11 v6a 10 v. [3:2] v5a v5a voltage range selection. 0x3 r/w 00 v5a 10 v. 01 v5a 2.5 v. 10 v5a 5 v. 11 v5a 10 v. [1:0] v4a v4a voltage range selection. 0x3 r/w 00 v4a 10 v. 01 v4a 2.5 v. 10 v4a 5 v. 11 v4a 10 v. reserved v4 a vo l ta g e r a n g e se l e cti o n 11: v4a = +/-10v. 10: v4a = +/-5v. 01: v4a = +/-2.5v. 00: v4a = +/-10v. v5 a vo l ta g e r a n g e se l e cti o n 11: v5a = +/-10v. 10: v5a = +/-5v. 01: v5a = +/-2.5v. 00: v5a = +/-10v. v7 a vo l ta g e r a n g e se l e cti o n 11: v7a = +/-10v. 10: v7a = +/-5v. 01: v7a = +/-2.5v. 00: v7a = +/-10v. v6 a vo l ta g e r a n g e se l e cti o n 11: v6a = +/-10v. 10: v6a = +/-5v. 01: v6a = +/-2.5v. 00: v6a = +/-10v. 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [1:0] v4a (r/w ) [8] reserved [3:2] v5a (r/w) [7:6] v7a (r/w) [5:4] v6a (r/w)
data sheet AD7617 rev. 0 | page 47 of 51 input range register b1 address: 0x06, reset: 0x00ff, name: input range register b1 table 26. bit descriptions for input range register b1 bits bit name settings description reset access [15:9] addressing bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved. 0x0 r/w [7:6] v3b v3b voltage range selection. 0x3 r/w 00 v3b 10 v. 01 v3b 2.5 v. 10 v3b 5 v. 11 v3b 10 v. [5:4] v2b v2b voltage range selection. 0x3 r/w 00 v2b 10 v. 01 v2b 2.5 v. 10 v2b 5 v. 11 v2b 10 v. [3:2] vb1 vb1 voltage range selection. 0x3 r/w 00 vb1 10 v. 01 vb1 2.5 v. 10 vb1 5 v. 11 vb1 10 v. [1:0] v0b v0b voltage range selection. 0x3 r/w 00 v0b 10 v. 01 v0b 2.5 v. 10 v0b 5 v. 11 v0b 10 v. v0b voltage range selection 11: v0b = +/-10v. 10: v0b = +/-5v. 01: v0b = +/-2.5v. 00: v0b = +/-10v. v1b voltage range selection 11: v1b = +/-10v. 10: v1b = +/-5v. 01: v1b = +/-2.5v. 00: v1b = +/-10v. v3b voltage range selection 11: v3b = +/-10v. 10: v3b = +/-5v. 01: v3b = +/-2.5v. 00: v3b = +/-10v. v2b voltage range selection 11: v2b = +/-10v. 10: v2b = +/-5v. 01: v2b = +/-2.5v. 00: v2b = +/-10v. 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w) [1:0] v0b (r/w) [8] reserved [3:2] v1b (r/w) [7:6] v3b (r/w) [5:4] v2b (r/w)
AD7617 data sheet rev. 0 | page 48 of 51 input range register b2 address: 0x07, reset: 0x00ff, name: input range register b2 table 27. bit descriptions for input range register b2 bits bit name settings description reset access [15:9] addressing bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved. 0x0 r/w [7:6] v7b v7b voltage range selection. 0x3 r/w 00 v7b 10 v. 01 v7b 2.5 v. 10 v7b 5 v. 11 v7b 10 v. [5:4] v6b v6b voltage range selection. 0x3 r/w 00 v6b 10 v. 01 v6b 2.5 v. 10 v6b 5 v. 11 v6b 10 v. [3:2] v5b v5b voltage range selection. 0x3 r/w 00 v5b 10 v. 01 v5b 2.5 v. 10 v5b 5 v. 11 v5b 10 v. [1:0] v4b v4b voltage range selection. 0x3 r/w 00 v4b 10 v. 01 v4b 2.5 v. 10 v4b 5 v. 11 v4b 10 v. v4b voltage range selection 11: v4b = +/-10v. 10: v4b = +/-5v. 01: v4b = +/-2.5v. 00: v4b = +/-10v. v5b voltage range selection 11: v5b = +/-10v. 10: v5b = +/-5v. 01: v5b = +/-2.5v. 00: v5b = +/-10v. v7b voltage range selection 11: v7b = +/-10v. 10: v7b = +/-5v. 01: v7b = +/-2.5v. 00: v7b = +/-10v. v6b voltage range selection 11: v6b = +/-10v. 10: v6b = +/-5v. 01: v6b = +/-2.5v. 00: v6b = +/-10v. 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w) [1:0] v4b (r/w) [8] reserved [3:2] v5b (r/w) [7:6] v7b (r/w) [5:4] v6b (r/w)
data sheet AD7617 rev. 0 | page 49 of 51 sequencer stack registers although the channel register defines the next channel for conversion (be it a diagnostic channel or pair of analog input chann els), to sample numerous analog input channels, the 32 sequencer stack registers offer a convenient solution. within the communication r egister, when the regaddr5 bit is set to logic 1, the contents of regadd r[4:0] specifies 1 of the 32 sequencer stack registers. within e ach sequencer stack register, the user can define a pair of analog inputs to sample simultaneously. the structure of the sequence forms a stack, in which each row represents two channels to convert simultaneously. the sequence begins with sequencer stack register 1 and cycles through to sequencer stack register 32. if bit d8 (the enable bit, ssrenx) within a sequencer stack register is set to 1, the sequence ends with the pair of analog inputs defined by that register, then returns to the firs t sequencer stack register, and resumes the cycle again. by default, the sequencer stack registers are programmed to cycle through channel v0a an d channel v0b to channel v7a and channel v7b. after a full or part ial reset is issued, the sequencer stack register reinitializes to cycle through channel v0a and channel v0b to channel v7a and channel v7b. address: 0x20 to 0x3f, reset: 0x0000, name: sequencer stack register 0 to sequencer stack register 31 table 28. bit descriptions for sequencer stack register 0 to sequencer stack register 31 bits bit name settings description reset access [15:9] addressing bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 ssren0 to ssren31 setting this bit to 0 instructs the adc to move to the next layer of the sequencer stack after converting the present channel pair. setting this bit to 1 defines that layer of the sequencer stack as the final layer in th e sequence. thereafter, the sequencer loops back to the first layer of the stack. 0x0 r/w [7:4] bsel0 to bsel31 channel selection bits for adc b channels. 0x0 1 r/w 0000 v0b. 0001 v1b. 0010 v2b. 0011 v3b. 0100 v4b. 0101 v5b. 0110 v6b. 0111 v7b. 1000 v cc . 1001 aldo. 1010 reserved. 1011 set the dedicated bits for digital interfac e communication self test function. when the conversion codes is read, code 0x2aaa is read out as the conversion code of channel a, and code 0x1555 is output as the conversion code of channel b. 1100 reserved. [3:0] asel0 to asel31 channel selection bits for adc a channels. settings are the same as for adc b. 0x0 1 r/w 1 after a full or partial reset is issued, the sequencer stack register is reinitialized to cycle through channel v0a and channe l v0b to channel v7a and channel v7b. the remaining 24 layers of the stac k are reinitialized to 0x0. channel selection bits for adc a channels defines final layer of stack channel selection bits for adc b channels 1100: reserved. 1011: adc b interface self test . 1010: reserved. ... 0010: selects channel v2b. 0001: selects channel v1b. 0000: selects channel v0b. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w) [3:0] asel[0:31] (r/w) [8] ssren[0:31] (r/w) [7:4] bsel[0:31] (r/w)
AD7617 data sheet rev. 0 | page 50 of 51 status register the status register is a 16 - bit read only register. if the status en bit or the crcen bit is set to l ogic 1 in the configuration register , the status register is read out at the end of all conversion words for the selected channels, including the self test channel if enabled in sequencer mode. consult the crc section and figure 69. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a , bits [3:0] b , bits [3:0] crc , bits [7:0] table 29. bit d escriptions for status register bit bit name settings description reset 1 access [ d15 : d12 ] a[3:0] channel i ndex for p revious c onversion r esult on c hannel a . n/a r [ d1 1: d8 ] b[3:0] channel i ndex for p revious c onversion r esult on c hannel b . n/a r [ d7 : d0 ] crc [7:0] crc calculation for t he previous conversion result(s) . refer to the crc section for further detail s . n/a r 1 n/a means not applicable.
data sheet AD7617 rev. 0 | page 51 of 51 outline d imensions figure 70 . 80 - l ead low profile quad flat p ackage [lqfp] (st - 80 - 2) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option AD7617 bstz ?40c to +125c 80 - lead low profile quad flat package [lqfp] st -80 -2 AD7617 bstz -rl ?40c to +125c 80 - lead low profile quad flat package [lqfp], 13 reel st -80 -2 eval - ad761 6 sdz use the ad7616 evaluation board 1 z = rohs compliant part. 2 the eval - ad7616sdz can evaluate the ad7616 and AD7617. compliant t o jedec s t andards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 t op view (pins down) pin 1 051706- a ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d16077 - 0 - 7/17(0)

▲Up To Search▲

Price & Availability of AD7617

	To Download AD7617 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .